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? 2011-2013 microchip technology inc. ds40001609b-page 1 pic16(l)f1508/9 high-performance risc cpu: ? c compiler optimized architecture ? only 49 instructions ? up to 8 kwords linear program memory addressing ? up to 512 bytes linear data memory addressing ? operating speed: - dc ? 20 mhz clock input - dc ? 200 ns instruction cycle ? interrupt capability with automatic context saving ? 16-level deep hardware stack with optional overflow/underflow reset ? direct, indirect and relative addressing modes: - two full 16-bit file select registers (fsrs) - fsrs can read program and data memory flexible oscillator structure: ? 16 mhz internal oscillator block: - factory calibrated to 1%, typical - software selectable frequency range from 16 mhz to 31 khz ? 31 khz low-power internal oscillator ? three external clock modes up to 20 mhz special microcontroller features: ? operating voltage range: - 1.8v to 3.6v (pic16lf1508/9) - 2.3v to 5.5v (pic16f1508/9) ? self-programmable under software control ? power-on reset (por) ? power-up timer (pwrt) ? programmable low-power brown-out reset (lpbor) ? extended watchdog timer (wdt): - programmable period from 1 ms to 256s ? programmable code protection ? in-circuit serial programming? (icsp?) via two pins ? enhanced low-voltage programming (lvp) ? in-circuit debug (icd) via two pins ? power-saving sleep mode: - low-power sleep mode - low-power bor (lpbor) ? integrated temperature indicator ? 128 bytes high-endurance flash - 100,000 write flash endurance (minimum) extreme low-power management with xlp (pic16lf1508/9): ? standby current: - 20 na @ 1.8v, typical ? watchdog timer current: - 260 na @ 1.8v, typical ? operating current: -30 ? a/mhz @ 1.8v, typical ? secondary oscillator current: - 700 na @ 32 khz, 1.8v, typical peripheral features: ? analog-to-digital converter (adc): - 10-bit resolution - 12 external channels - 3 internal channels: - fixed voltage reference - digital-to-analog converter (dac) - temperature indicator channel - auto acquisition capability - conversion available during sleep ? 5-bit digital-to-analog converter (dac): - output available externally - positive reference selection - internal connections to comparators and adc ? 2 comparators: - rail-to-rail inputs - power mode control - software controllable hysteresis ? voltage reference module: - fixed voltage reference (fvr) with 1.024v, 2.048v and 4.096v output levels - 1 rail-to-rail resistive 5-bit dac with positive reference selection ? 18 i/o pins (1 input-only pin): - high current sink/source 25 ma/25 ma - individually programmable weak pull-ups - individually programmable interrupt-on-change (ioc) pins ? timer0: 8-bit timer/counter with 8-bit programmable prescaler ? enhanced timer1: - 16-bit timer/counter with prescaler - external gate input mode ? timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler ? four 10-bit pwm modules 20-pin flash, 8-bit microcontrollers with xlp technology
pic16(l)f1508/9 ds40001609b-page 2 ? 2011-2013 microchip technology inc. peripheral features (continued): ? master synchronous serial port (mssp) with spi and i 2 c? with: - 7-bit address masking - smbus/pmbus? compatibility ? enhanced universal synchronous asynchronous receiver transmitter (eusart) - rs-232, rs-485 and lin compatible - auto-baud detect - auto-wake-up on start ? 4 configurable logic cell (clc) modules: - 16 selectable input source signals - four inputs per module - software control of combinational/sequential logic/state/clock functions - and/or/xor/d flop/d latch/sr/jk - inputs from external and internal sources - output available to pins and peripherals - operation while in sleep ? numerically controlled oscillator (nco): - 20-bit accumulator - 16-bit increment - true linear frequency control - high-speed clock input - selectable output modes - fixed duty cycle (fdc) mode - pulse frequency (pf) mode ? complementary waveform generator (cwg): - 8 selectable signal sources - selectable falling and rising edge dead-band control - polarity control - 4 auto-shutdown sources - multiple input sources: pwm, clc, nco pic12(l)f1501/pic16(l)f150x family types device data sheet index program memory flash (words) data sram (bytes) i/o?s (2) 10-bit adc (ch) comparators dac timers (8/16-bit) pwm eusart mssp (i 2 c?/spi) cwg clc nco debug (1) xlp pic12(l)f1501 (1) 1024 64 6 4 1 1 2/1 4 ? ? 1 2 1 h ? pic16(l)f1503 (2) 2048 128 12 8 2 1 2/1 4 ? 1 1 2 1 h ? pic16(l)f1507 (3) 2048 128 18 12 ? ? 2/1 4 ? ? 1 2 1 h ? pic16(l)f1508 (4) 4096 256 18 12 2 1 2/1 4 1 1 1 4 1 i/h y pic16(l)f1509 (4) 8192 512 18 12 2 1 2/1 4 1 1 1 4 1 i/h y note 1: debugging methods: (i) ? integrated on chip; (h) ? using debug header; e ? using emulation header. 2: one pin is input-only. data sheet index: (unshaded devices are described in this document.) 1: ds41615 pic12(l)f1501 data sheet, 8-pin flash, 8-bit microcontrollers. 2: ds41607 pic16(l)f1503 data sheet, 14-pin flash, 8-bit microcontrollers. 3: ds41586 pic16(l)f1507 data sheet, 20-pin flash, 8-bit microcontrollers. 4: ds40001609 pic16(l)f1508/9 data sheet, 20-pin flash, 8-bit microcontrollers. note: for other small form-factor package availability and marking information, please visit http://www.microchip.com/packaging or contact your local sales office.
? 2011-2013 microchip technology inc. ds40001609b-page 3 pic16(l)f1508/9 pin diagrams pin diagram ? 20-pin pdip, soic, ssop pin diagram ? 20-pin qfn pic16f1508/9 pic16lf1508/9 1 2 3 4 14 13 12 11 5 6 7 10 9 8 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 v ss ra0/icspdat ra1/icspclk ra2 rc0 rc1 rc2 rc3 note: see tab l e 1 for location of all peripheral functions. 18 17 16 15 20 19 rc6 rc7 rb7 rb4 rb5 rb6 pic16f1508/9 pic16lf1508/9 note 1: see ta b l e 1 for location of all peripheral functions. 2: it is recommended that the exposed bottom pad be connected to v ss . 15 ra1/icspclk ra2 rc0 rc1 rc2 11 12 13 14 6 7 rc7 rb7 rb4 rb5 rb6 8 9 10 2 3 1 18 19 20 16 17 5 4 v dd ra5 ra4 mclr /v pp /ra3 rc5 rc4 rc3 rc6 v ss ra0/icspdat
pic16(l)f1508/9 ds40001609b-page 4 ? 2011-2013 microchip technology inc. pin allocation table table 1: 20-pin allocation table (pic16(l)f1508/9) i/o 20-pin pdip/soic/ssop 20-pin qfn adc reference comparator timers eusart mssp cwg nco clc pwm interrupt pull-up basic ra0 19 16 an0 dac1out1 c1in+ ? ? ? ? ? ? ? ioc y icspdat icddat ra1 18 15 an1 v ref + c1in0- c2in0- ??? ? ? clc4in1 ? ioc y icspclk icdclk ra2 17 14 an2 dac1out2 c1out t0cki ? ? cwg1flt ? clc1 pwm3 int/ ioc y ? ra3 4 1 ? ? ? t1g (1) ?ss (1) ? ? clc1in0 ? ioc y mclr v pp ra4 3 20 an3 ? ? sosco t1g ? ? ? ? ? ? ioc y clkout osc2 ra5 2 19 ? ? ? sosci t1cki ?? ? nco1clk ? ? ioc y clkin osc1 rb4 13 10 an10 ? ? ? ? sda/sdi ? ? clc3in0 ? ioc y ? rb5 12 9 an11 ? ? ?rx/dt? ? ? clc4in0 ? ioc y ? rb6 11 8 ? ? ? ? ? scl/sck ? ? ? ? ioc y ? rb7 10 7 ? ? ? ?tx/ck? ? ? clc3 ? ioc y ? rc0 16 13 an4 ? c2in+ ? ? ? ? ? clc2 ? ? ? ? rc1 15 12 an5 ? c1in1- c2in1- ??? ? nco1 ? pwm4 ? ? ? rc2 14 11 an6 ? c1in2- c2in2- ? ? ? ? ? ? ? ? ? ? rc3 7 4 an7 ? c1in3- c2in3- ??? ? ? clc2in0 pwm2 ? ? ? rc4 6 3 ? ? c2out ? ? ? cwg1b ? clc4 clc2in1 ? ? ? ? rc5 5 2 ? ? ? ??? cwg1a ? clc1 (1) pwm1 ? ? ? rc6 8 5 an8 ? ? ? ? ss ? nco1 (1) clc3in1 ? ? ? ? rc7 9 6 an9 ? ? ??sdo ? ? clc1in1 ? ? ? ? v dd 1 18 ? ? ? ? ? ? ? ? ? ? ? ? v dd v ss 20 17 ? ? ? ? ? ? ? ? ? ? ? ? v ss note 1: alternate pin function selected with the apfcon ( register 11-1 ) register.
? 2011-2013 microchip technology inc. ds40001609b-page 5 pic16(l)f1508/9 table of contents 1.0 device overview ............................................................................................................. ............................................................. 7 2.0 enhanced mid-range cpu ...................................................................................................... .................................................. 13 3.0 memory organization ......................................................................................................... ........................................................ 15 4.0 device configuration ........................................................................................................ .......................................................... 41 5.0 oscillator module (with fail-safe clock monitor)............................................................................ ........................................... 47 6.0 resets ...................................................................................................................... .................................................................. 63 7.0 interrupts .................................................................................................................. .................................................................. 71 8.0 power-down mode (sleep) ..................................................................................................... ................................................... 85 9.0 watchdog timer (wdt) ........................................................................................................ ..................................................... 89 10.0 flash program memory control ............................................................................................... .................................................. 93 11.0 i/o ports .................................................................................................................. ................................................................. 109 12.0 interrupt-on-change ........................................................................................................ ........................................................ 123 13.0 fixed voltage reference (fvr) .............................................................................................. ................................................. 129 14.0 temperature indicator module ............................................................................................... .................................................. 131 15.0 analog-to-digital converter (adc) module ................................................................................... ........................................... 133 16.0 5-bit digital-to-analog converter (dac) module............................................................................. ......................................... 147 17.0 comparator module.......................................................................................................... ........................................................ 151 18.0 timer0 module .............................................................................................................. ........................................................... 159 19.0 timer1 module with gate control............................................................................................ ................................................. 163 20.0 timer2 module .............................................................................................................. ........................................................... 175 21.0 master synchronous serial port (mssp) module ............................................................................... ..................................... 179 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) .................................................. ............. 235 23.0 pulse width modulation (pwm) module........................................................................................ ........................................... 263 24.0 configurable logic cell (clc).............................................................................................. .................................................... 269 25.0 numerically controlled oscillator (nco) module ............................................................................. ........................................ 285 26.0 complementary waveform generator (cwg) module .............................................................................. .............................. 295 27.0 in-circuit serial programming? (icsp?) ..................................................................................... .......................................... 307 28.0 instruction set summary .................................................................................................... ...................................................... 309 29.0 electrical specifications.................................................................................................. .......................................................... 323 30.0 dc and ac characteristics graphs and charts ................................................................................ ....................................... 353 31.0 development support........................................................................................................ ....................................................... 395 32.0 packaging information...................................................................................................... ........................................................ 399 appendix a: data sheet revision history........................................................................................ .................................................. 409 index .......................................................................................................................... ........................................................................ 411 the microchip web site ......................................................................................................... ............................................................ 417 customer change notification service ........................................................................................... ................................................... 417 customer support............................................................................................................... ............................................................... 418 reader response ................................................................................................................ .............................................................. 418 product identification system .................................................................................................. .......................................................... 419
pic16(l)f1508/9 ds40001609b-page 6 ? 2011-2013 microchip technology inc. to our valued customers it is our intention to provide our valued customers with the be st documentation possible to ensure successful use of your micro chip products. to this end, we will continue to improve our publications to better suit your needs. our publications will be refined and enhanced as new volumes and updates are introduced. if you have any questions or comments regardi ng this publication, please contact the marketing communications department via e-mail at docerrors@microchip.com or fax the reader response form in the back of this data sheet to (480) 792-4150. we welcome your feedback. most current data sheet to obtain the most up-to-date version of this data s heet, please register at our worldwide web site at: http://www.microchip.com you can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page . the last character of the literature number is the vers ion number, (e.g., ds30000a is version a of document ds30000). errata an errata sheet, describing minor operational differences fr om the data sheet and recommended workarounds, may exist for curren t devices. as device/documentation issues become known to us, we will publish an errata sheet. the errata will specify the revisi on of silicon and revision of document to which it applies. to determine if an errata sheet exists for a particular device, please check with one of the following: ? microchip?s worldwide web site; http://www.microchip.com ? your local microchip sales office (see last page) when contacting a sales office, please specify which device, re vision of silicon and data sheet (include literature number) you are using. customer notification system register on our web site at www.microchip.com to receive the most current information on all of our products.
? 2011-2013 microchip technology inc. ds40001609b-page 7 pic16(l)f1508/9 1.0 device overview the pic16(l)f1508/9 are described within this data sheet. figure 1-1 shows a block diagram of the pic16(l)f1508/9 devices. tables 1-2 shows the pinout descriptions. reference tab l e 1 - 1 for peripherals available per device. table 1-1: device peripheral summary peripheral pic12f1501 pic12lf1501 pic16f1503 pic16lf1503 PIC16F1507 pic16lf1507 pic16f1508 pic16lf1508 pic16f1509 pic16lf1509 analog-to-digital converter (adc) complementary wave generator (cwg) digital-to-analog converter (dac) enhanced universal synchronous/asynchronous receiver/transmitter (eusart) fixed voltage reference (fvr) numerically controlled oscillator (nco) temperature indicator comparators c1 c2 configurable logic cell (clc) clc1 clc2 clc3 clc4 master synchronous serial ports mssp1 pwm modules pwm1 pwm2 pwm3 pwm4 timers timer0 timer1 timer2
pic16(l)f1508/9 ds40001609b-page 8 ? 2011-2013 microchip technology inc. figure 1-1: pic16(l)f1508/9 block diagram portc note 1: see applicable chapters for more information on peripherals. 2: see ta b l e 1 - 1 for peripherals available on specific devices. cpu program flash memory ram timing generation intrc oscillator mclr ( figure 2-1 ) nco1 pwm4 timer2 timer1 timer0 clc4 pwm1 pwm2 pwm3 porta cwg1 clc3 adc 10-bit fvr te m p . indicator osc1/clkin osc2/clkout mssp1 c2 c1 dac portb clc2 clc1 eusart
? 2011-2013 microchip technology inc. ds40001609b-page 9 pic16(l)f1508/9 table 1-2: pic16(l)f1508/9 pinout description name function input type output type description ra0/an0/c1in+/dac1out1/ icspdat/icddat ra0 ttl cmos general purpose i/o. an0 an ? adc channel input. c1in+ an ? comparator positive input. dac1out1 ? an digital-to-analog converter output. icspdat st cmos icsp? data i/o. icddat st cmos in-circuit debug data. ra1/an1/clc4in1/v ref +/ c1in0-/c2in0-/icspclk/ icdclk ra1 ttl cmos general purpose i/o. an1 an ? adc channel input. clc4in1 st ? configurable logic cell source input. v ref + an ? adc positive voltage reference input. c1in0- an ? comparator negative input. c2in0- an ? comparator negative input. icspclk st ? icsp programming clock. icdclk st ? in-circuit debug clock. ra2/an2/c1out/dac1out2/ t0cki/int/pwm3/clc1/ cwg1flt ra2 st cmos general purpose i/o. an2 an ? adc channel input. c1out ? cmos comparator output. dac1out2 ? an digital-to-analog converter output. t0cki st ? timer0 clock input. int st ? external interrupt. pwm3 ? cmos pwm output. clc1 ? cmos configurable logic cell source output. cwg1flt st ? complementary waveform generator fault input. ra3/clc1in0/v pp /t1g (1) /ss (1) / mclr ra3 ttl ? general purpose input with ioc and wpu. clc1in0 st ? configurable logic cell source input. v pp hv ? programming voltage. t1g st ? timer1 gate input. ss st ? slave select input. mclr st ? master clear with internal pull-up. ra4/an3/sosco/ clkout/t1g ra4 ttl cmos general purpose i/o. an3 an ? adc channel input. sosco xtal xtal secondary oscillator connection. clkout ? cmos f osc /4 output. t1g st ? timer1 gate input. ra5/clkin/t1cki/nco1clk/ sosci ra5 ttl cmos general purpose i/o. clkin cmos ? external clock input (ec mode). t1cki st ? timer1 clock input. nco1clk st ? numerically controlled oscillator clock source input. sosci xtal xtal secondary oscillator connection. legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 11-1 ) register.
pic16(l)f1508/9 ds40001609b-page 10 ? 2011-2013 microchip technology inc. rb4/an10/clc3in0/sda/sdi rb4 ttl cmos general purpose i/o. an10 an ? adc channel input. clc3in0 st ? configurable logic cell source input. sda i 2 codi 2 c data input/output. sdi cmos ? spi data input. rb5/an11/clc4in0/rx/dt rb5 ttl cmos general purpose i/o. an11 an ? adc channel input. clc4in0 st ? configurable logic cell source input. rx st ? usart asynchronous input. dt st cmos usart synchronous data. rb6/scl/sck rb6 ttl cmos general purpose i/o. scl i 2 codi 2 c? clock. sck st cmos spi clock. rb7/clc3/tx/ck rb7 ttl cmos general purpose i/o. clc3 ? cmos configurable logic cell source output. tx ? cmos usart asynchronous transmit. ck st cmos usart synchronous clock. rc0/an4/clc2/c2in+ rc0 ttl cmos general purpose i/o. an4 an ? adc channel input. clc2 ? cmos configurable logic cell source output. c2in+ an ? comparator positive input. rc1/an5/c1in1-/c2in1-/pwm4/ nco1 rc1 ttl cmos general purpose i/o. an5 an ? adc channel input. c1in1- an ? comparator negative input. c2in1- an ? comparator negative input. pwm4 ? cmos pwm output. nco1 ? cmos numerically controlled oscillator is source output. rc2/an6/c1in2-/c2in2- rc2 ttl cmos general purpose i/o. an6 an ? adc channel input. c1in2- an ? comparator negative input. c2in2- an ? comparator negative input. rc3/an7/c1in3-/c2in3-/pwm2/ clc2in0 rc3 ttl cmos general purpose i/o. an7 an ? adc channel input. c1in3- an ? comparator negative input. c2in3- an ? comparator negative input. pwm2 ? cmos pwm output. clc2in0 st ? configurable logic cell source input. rc4/c2out/clc2in1/clc4/ cwg1b rc4 ttl cmos general purpose i/o. c2out ? cmos comparator output. clc2in1 st ? configurable logic cell source input. clc4 ? cmos configurable logic cell source output. cwg1b ? cmos cwg complementary output. table 1-2: pic16(l)f1508/9 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 11-1 ) register.
? 2011-2013 microchip technology inc. ds40001609b-page 11 pic16(l)f1508/9 rc5/pwm1/clc1 (1) / cwg1a rc5 ttl cmos general purpose i/o. pwm1 ? cmos pwm output. clc1 ? cmos configurable logic cell source output. cwg1a ? cmos cwg primary output. rc6/an8/nco1 (1) /clc3in1/ ss rc6 ttl cmos general purpose i/o. an8 an ? adc channel input. nco1 ? cmos numerically controlled oscillator source output. clc3in1 st ? configurable logic cell source input. ss st ? slave select input. rc7/an9/clc1in1/sdo rc7 ttl cmos general purpose i/o. an9 an ? adc channel input. clc1in1 st ? configurable logic cell source input. sdo ? cmos spi data output. v dd v dd power ? positive supply. v ss v ss power ? ground reference. table 1-2: pic16(l)f1508/9 pinout description (continued) name function input type output type description legend: an = analog input or output cmos = cmos compatible input or output od = open drain ttl = ttl compatible input st = schmitt trigger input with cmos levels i 2 c? = schmitt trigger input with i 2 c hv = high voltage xtal = crystal levels note 1: alternate pin function selected with the apfcon ( register 11-1 ) register.
pic16(l)f1508/9 ds40001609b-page 12 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 13 pic16(l)f1508/9 2.0 enhanced mid-range cpu this family of devices contain an enhanced mid-range 8-bit cpu core. the cpu has 49 instructions. interrupt capability includes automatic context saving. the hardware stack is 16 levels deep and has overflow and underflow reset capability. direct, indirect, and relative addressing modes are available. two file select registers (fsrs) provide the ability to read program and data memory. ? automatic interrupt context saving ? 16-level stack with overflow and underflow ? file select registers ? instruction set figure 2-1: core block diagram data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 12 addr mux fsr reg status reg mux alu instruction decode & control timing generation clkin clkout 8 8 12 3 internal oscillator block configuration data bus 8 14 program bus instruction reg program counter 8 level stack (13-bit) direct addr 7 addr mux fsr reg status reg mux alu w reg instruction decode & control timing generation 8 8 3 internal oscillator block configuration 15 data bus 8 14 program bus instruction reg program counter 16-level stack (15-bit) direct addr 7 ram addr addr mux indirect addr fsr0 reg status reg mux alu instruction decode and control timing generation 8 8 3 internal oscillator block configuration flash program memory ram fsr reg fsr reg fsr1 reg 15 15 mux 15 program memory read (pmr) 12 fsr reg fsr reg bsr reg 5 power-up timer power-on reset watchdog timer v dd brown-out reset v ss v dd v ss v dd v ss
pic16(l)f1508/9 ds40001609b-page 14 ? 2011-2013 microchip technology inc. 2.1 automatic interrupt context saving during interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. this saves stack space and user code. see section 7.5 ?automatic context saving? , for more information. 2.2 16-level stack with overflow and underflow these devices have a hardware stack memory 15 bits wide and 16 words deep. a stack overflow or under- flow will set the appropriate bit (stkovf or stkunf) in the pcon register, and if enabled, will cause a soft- ware reset. see section section 3.4 ?stack? for more details. 2.3 file select registers there are two 16-bit file select registers (fsr). fsrs can access all file registers and program memory, which allows one data pointer for all memory. when an fsr points to program memory, there is one additional instruction cycle in instructions using indf to allow the data to be fetched. general purpose memory can now also be addressed linearly, providing the ability to access contiguous data larger than 80 bytes. there are also new instructions to support the fsrs. see section 3.5 ?indirect addressing? for more details. 2.4 instruction set there are 49 instructions for the enhanced mid-range cpu to support the features of the cpu. see section 28.0 ?instruction set summary? for more details.
? 2011-2013 microchip technology inc. ds40001609b-page 15 pic16(l)f1508/9 3.0 memory organization these devices contain the following types of memory: ? program memory - configuration words - device id -user id - flash program memory ? data memory - core registers - special function registers - general purpose ram - common ram the following features are associated with access and control of program memory and data memory: ? pcl and pclath ?stack ? indirect addressing 3.1 program memory organization the enhanced mid-range core has a 15-bit program counter capable of addressing a 32k x 14 program memory space. table 3-1 shows the memory sizes implemented. accessing a location above these boundaries will cause a wrap-around within the implemented memory space. the reset vector is at 0000h and the interrupt vector is at 0004h (see figure 3-1 ). table 3-1: device sizes and addresses device program memory space (words) last program memory address high-endurance flash memory address range (1) pic16f1508 pic16lf1508 4,096 0fffh 0f80h-0fffh pic16f1509 pic16lf1509 8,192 1fffh 1f80h-1fffh note 1: high-endurance flash applies to low byte of each address in the range.
pic16(l)f1508/9 ds40001609b-page 16 ? 2011-2013 microchip technology inc. figure 3-1: program memory map and stack for pic16(l)f1508 figure 3-2: program memory map and stack for pic16(l)f1509 pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector call , callw return , retlw stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 1 interrupt, retfie pc<14:0> 15 0000h 0004h stack level 0 stack level 15 reset vector interrupt vector stack level 1 0005h on-chip program memory page 0 07ffh rollover to page 0 0800h 0fffh 1000h 7fffh page 1 rollover to page 3 page 2 page 3 17ffh 1800h 1fffh 2000h call , callw return , retlw interrupt, retfie
? 2011-2013 microchip technology inc. ds40001609b-page 17 pic16(l)f1508/9 3.1.1 reading program memory as data there are two methods of accessing constants in pro- gram memory. the first method is to use tables of retlw instructions. the second method is to set an fsr to point to the program memory. 3.1.1.1 retlw instruction the retlw instruction can be used to provide access to tables of constants. the recommended way to cre- ate such a table is shown in example 3-1 . example 3-1: retlw instruction the brw instruction makes this type of table very sim- ple to implement. if your code must remain portable with previous generations of microcontrollers, then the brw instruction is not available so the older table read method must be used. 3.1.1.2 indirect read with fsr the program memory can be accessed as data by set- ting bit 7 of the fsrxh register and reading the match- ing indfx register. the moviw instruction will place the lower eight bits of the addressed word in the w register. writes to the program memory cannot be performed via the indf registers. instructions that access the pro- gram memory via the fsr require one extra instruction cycle to complete. example 3-2 demonstrates access- ing the program memory via an fsr. the high operator will set bit<7> if a label points to a location in program memory. example 3-2: accessing program memory via fsr constants brw ;add index in w to ;program counter to ;select data retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw data_index call constants ;? the constant is in w constants retlw data0 ;index0 data retlw data1 ;index1 data retlw data2 retlw data3 my_function ;? lots of code? movlw low constants movwf fsr1l movlw high constants movwf fsr1h moviw 0[fsr1] ;the program memory is in w
pic16(l)f1508/9 ds40001609b-page 18 ? 2011-2013 microchip technology inc. 3.2 data memory organization the data memory is partitioned in 32 memory banks with 128 bytes in a bank. each bank consists of ( figure 3-3 ): ? 12 core registers ? 20 special function registers (sfr) ? up to 80 bytes of general purpose ram (gpr) ? 16 bytes of common ram the active bank is selected by writing the bank number into the bank select register (bsr). unimplemented memory will read as ? 0 ?. all data memory can be accessed either directly (via instructions that use the file registers) or indirectly via the two file select registers (fsr). see section 3.5 ?indirect addressing? for more information. data memory uses a 12-bit address. the upper seven bits of the address define the bank address and the lower five bits select the registers/ram in that bank. 3.2.1 core registers the core registers contain the registers that directly affect the basic operation. the core registers occupy the first 12 addresses of every data memory bank (addresses x00h/x08h through x0bh/x8bh). these registers are listed below in ta b l e 3 - 2 . for detailed information, see tab l e 3 - 8 . table 3-2: core registers addresses bankx x00h or x80h indf0 x01h or x81h indf1 x02h or x82h pcl x03h or x83h status x04h or x84h fsr0l x05h or x85h fsr0h x06h or x86h fsr1l x07h or x87h fsr1h x08h or x88h bsr x09h or x89h wreg x0ah or x8ah pclath x0bh or x8bh intcon
? 2011-2013 microchip technology inc. ds40001609b-page 19 pic16(l)f1508/9 3.2.1.1 status register the status register, shown in register 3-1 , contains: ? the arithmetic status of the alu ? the reset status the status register can be the destination for any instruction, like any other register. if the status register is the destination for an instruction that affects the z, dc or c bits, then the write to these three bits is disabled. these bits are set or cleared according to the device logic. furthermore, the to and pd bits are not writable. therefore, the result of an instruction with the status register as destination may be different than intended. for example, clrf status will clear the upper three bits and set the z bit. this leaves the status register as ? 000u u1uu ? (where u = unchanged). it is recommended, therefore, that only bcf, bsf, swapf and movwf instructions are used to alter the status register, because these instructions do not affect any status bits. for other instructions not affecting any status bits (refer to section 28.0 ?instruction set summary? ). note 1: the c and dc bits operate as borrow and digit borrow out bits, respectively, in subtraction. register 3-1: status: status register u-0 u-0 u-0 r-1/q r-1/q r/w-0/u r/w-0/u r/w-0/u ? ? ? to pd zdc (1) c (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-5 unimplemented: read as ? 0 ? bit 4 to : time-out bit 1 = after power-up, clrwdt instruction or sleep instruction 0 = a wdt time-out occurred bit 3 pd : power-down bit 1 = after power-up or by the clrwdt instruction 0 = by execution of the sleep instruction bit 2 z: zero bit 1 = the result of an arithmetic or logic operation is zero 0 = the result of an arithmetic or logic operation is not zero bit 1 dc: digit carry/digit borrow bit ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the 4th low-order bit of the result occurred 0 = no carry-out from the 4th low-order bit of the result bit 0 c: carry/borrow bit (1) ( addwf , addlw , sublw , subwf instructions) (1) 1 = a carry-out from the most significant bit of the result occurred 0 = no carry-out from the most significant bit of the result occurred note 1: for borrow , the polarity is reversed. a subtraction is executed by adding the two?s complement of the second operand. for rotate ( rrf , rlf ) instructions, this bit is loaded with either the high-order or low-order bit of the source register.
pic16(l)f1508/9 ds40001609b-page 20 ? 2011-2013 microchip technology inc. 3.2.2 special function register the special function registers are registers used by the application to control the desired operation of peripheral functions in the device. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). the registers associated with the operation of the peripherals are described in the appro- priate peripheral chapter of this data sheet. 3.2.3 general purpose ram there are up to 80 bytes of gpr in each data memory bank. the special function registers occupy the 20 bytes after the core registers of every data memory bank (addresses x0ch/x8ch through x1fh/x9fh). 3.2.3.1 linear access to gpr the general purpose ram can be accessed in a non-banked method via the fsrs. this can simplify access to large memory structures. see section 3.5.2 ?linear data memory? for more information. 3.2.4 common ram there are 16 bytes of common ram accessible from all banks. figure 3-3: banked memory partitioning 3.2.5 device memory maps the memory maps for pic16(l)f1508/9 are as shown in table 3-5 and ta b l e 3 - 6 . 0bh 0ch 1fh 20h 6fh 70h 7fh 00h common ram (16 bytes) general purpose ram (80 bytes maximum) core registers (12 bytes) special function registers (20 bytes maximum) memory region 7-bit bank offset
? 2011-2013 microchip technology inc. ds40001609b-page 21 pic16(l)f1508/9 table 3-3: pic16(l)f1508 memory map, bank 1-7 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch wpua 28ch ? 30ch ? 38ch ? 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh ? 30dh ? 38dh ? 00eh portc 08eh trisc 10eh latc 18eh anselc 20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h ?090h ?110h ?190h ?210h ?290h ? 310h ? 390h ? 011h pir1 091h pie1 111h cm1con0 191h pmadrl 211h ssp1buf 291h ? 311h ? 391h iocap 012h pir2 092h pie2 112h cm1con1 192h pmadrh 212h ssp1add 292h ? 312h ? 392h iocan 013h pir3 093h pie3 113h cm2con0 193h pmdatl 213h ssp1msk 293h ? 313h ? 393h iocaf 014h ?094h ? 114h cm2con1 194h pmdath 214h ssp1stat 294h ? 314h ? 394h iocbp 015h tmr0 095h option_reg 115h cmout 195h pmcon1 215h ssp1con1 295h ? 315h ? 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ssp1con2 296h ? 316h ? 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon 217h ssp1con3 297h ? 317h ? 397h ? 018h t1con 098h ?118h dac1con0 198h ?218h ? 298h ? 318h ? 398h ? 019h t1gcon 099h osccon 119h dac1con1 199h rcreg 219h ?299h ? 319h ? 399h ? 01ah tmr2 09ah oscstat 11ah ?19ah txreg 21ah ?29ah ?31ah ?39ah ? 01bh pr2 09bhadresl11bh ?19bh spbrg 21bh ?29bh ?31bh ? 39bh ? 01ch t2con 09ch adresh 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 11dh apfcon 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 11eh ? 19eh txsta 21eh ? 29eh ? 31eh ? 39eh ? 01fh ? 09fh adcon2 11fh ?19fh baudcon 21fh ? 29fh ? 31fh ? 39fh ? 020h general purpose register 80 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h unimplemented read as ? 0 ? 220h unimplemented read as ? 0 ? 2a0h unimplemented read as ? 0 ? 320h unimplemented read as ? 0 ? 3a0h unimplemented read as ? 0 ? 0efh 06fh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram 0f0h common ram (accesses 70h ? 7fh) 170h common ram (accesses 70h ? 7fh) 1f0h common ram (accesses 70h ? 7fh) 270h common ram (accesses 70h ? 7fh) 2f0h common ram (accesses 70h ? 7fh) 370h common ram (accesses 70h ? 7fh) 3f0h common ram (accesses 70h ? 7fh) 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh legend: = unimplemented data memory locations, read as ? 0 ?.
pic16(l)f1508/9 ds40001609b-page 22 ? 2011-2013 microchip technology inc. table 3-4: pic16(l)f1509 memory map, bank 1-7 bank 0 bank 1 bank 2 bank 3 bank 4 bank 5 bank 6 bank 7 000h core registers ( ta b l e 3 - 2 ) 080h core registers ( ta b l e 3 - 2 ) 100h core registers ( table 3-2 ) 180h core registers ( table 3-2 ) 200h core registers ( table 3-2 ) 280h core registers ( table 3-2 ) 300h core registers ( table 3-2 ) 380h core registers ( table 3-2 ) 00bh 08bh 10bh 18bh 20bh 28bh 30bh 38bh 00ch porta 08ch trisa 10ch lata 18ch ansela 20ch wpua 28ch ? 30ch ? 38ch ? 00dh portb 08dh trisb 10dh latb 18dh anselb 20dh wpub 28dh ? 30dh ? 38dh ? 00eh portc 08eh trisc 10eh latc 18eh anselc 20eh ?28eh ?30eh ?38eh ? 00fh ?08fh ?10fh ?18fh ?20fh ?28fh ?30fh ?38fh ? 010h ?090h ?110h ?190h ?210h ?290h ? 310h ? 390h ? 011h pir1 091h pie1 111h cm1con0 191h pmadrl 211h ssp1buf 291h ? 311h ? 391h iocap 012h pir2 092h pie2 112h cm1con1 192h pmadrh 212h ssp1add 292h ? 312h ? 392h iocan 013h pir3 093h pie3 113h cm2con0 193h pmdatl 213h ssp1msk 293h ? 313h ? 393h iocaf 014h ?094h ? 114h cm2con1 194h pmdath 214h ssp1stat 294h ? 314h ? 394h iocbp 015h tmr0 095h option_reg 115h cmout 195h pmcon1 215h ssp1con1 295h ? 315h ? 395h iocbn 016h tmr1l 096h pcon 116h borcon 196h pmcon2 216h ssp1con2 296h ? 316h ? 396h iocbf 017h tmr1h 097h wdtcon 117h fvrcon 197h vregcon 217h ssp1con3 297h ? 317h ? 397h ? 018h t1con 098h ?118h dac1con0 198h ?218h ? 298h ? 318h ? 398h ? 019h t1gcon 099h osccon 119h dac1con1 199h rcreg 219h ?299h ? 319h ? 399h ? 01ah tmr2 09ah oscstat 11ah ?19ah txreg 21ah ?29ah ?31ah ?39ah ? 01bh pr2 09bhadresl11bh ?19bh spbrg 21bh ?29bh ?31bh ? 39bh ? 01ch t2con 09ch adresh 11ch ? 19ch spbrgh 21ch ? 29ch ? 31ch ? 39ch ? 01dh ? 09dh adcon0 11dh apfcon 19dh rcsta 21dh ? 29dh ? 31dh ? 39dh ? 01eh ? 09eh adcon1 11eh ? 19eh txsta 21eh ? 29eh ? 31eh ? 39eh ? 01fh ? 09fh adcon2 11fh ?19fh baudcon 21fh ? 29fh ? 31fh ? 39fh ? 020h general purpose register 80 bytes 0a0h general purpose register 80 bytes 120h general purpose register 80 bytes 1a0h general purpose register 80 bytes 220h general purpose register 80 bytes 2a0h general purpose register 80 bytes 320h general purpose register 16bytes 3a0h unimplemented read as ? 0 ? unimplemented read as ? 0 ? 0efh 06fh 16fh 1efh 26fh 2efh 36fh 3efh 070h common ram 0f0h accesses 70h ? 7fh 170h accesses 70h ? 7fh 1f0h accesses 70h ? 7fh 270h accesses 70h ? 7fh 2f0h accesses 70h ? 7fh 370h accesses 70h ? 7fh 3f0h accesses 70h ? 7fh 07fh 0ffh 17fh 1ffh 27fh 2ffh 37fh 3ffh legend: = unimplemented data memory locations, read as ? 0 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 23 pic16(l)f1508/9 table 3-5: pic16(l)f1508/9 memory map, bank 8-23 bank 8 bank 9 bank 10 bank 11 bank 12 bank 13 bank 14 bank 15 400h 40bh core registers ( ta b l e 3 - 2 ) 480h 48bh core registers ( ta b l e 3 - 2 ) 500h 50bh core registers ( table 3-2 ) 580h 58bh core registers ( table 3-2 ) 600h 60bh core registers ( table 3-2 ) 680h 68bh core registers ( table 3-2 ) 700h 70bh core registers ( table 3-2 ) 780h 78bh core registers ( table 3-2 ) 40ch ? 48ch ? 50ch ? 58ch ? 60ch ? 68ch ? 70ch ? 78ch ? 40dh ? 48dh ? 50dh ? 58dh ? 60dh ? 68dh ? 70dh ? 78dh ? 40eh ?48eh ?50eh ?58eh ?60eh ?68eh ?70eh ?78eh ? 40fh ?48fh ?50fh ?58fh ?60fh ?68fh ?70fh ?78fh ? 410h ?490h ?510h ?590h ?610h ?690h ? 710h ? 790h ? 411h ?491h ?511h ?591h ? 611h pwm1dcl 691h cwg1dbr 711h ? 791h ? 412h ?492h ?512h ?592h ? 612h pwm1dch 692h cwg1dbf 712h ? 792h ? 413h ?493h ?513h ?593h ? 613h pwm1con 693h cwg1con0 713h ? 793h ? 414h ?494h ?514h ?594h ? 614h pwm2dcl 694h cwg1con1 714h ? 794h ? 415h ?495h ?515h ?595h ? 615h pwm2dch 695h cwg1con2 715h ? 795h ? 416h ?496h ?516h ?596h ? 616h pwm2con 696h ? 716h ? 796h ? 417h ?497h ?517h ?597h ? 617h pwm3dcl 697h ? 717h ? 797h ? 418h ? 498h nco1accl 518h ?598h ? 618h pwm3dch 698h ? 718h ? 798h ? 419h ? 499h nco1acch 519h ?599h ? 619h pwm3con 699h ? 719h ? 799h ? 41ah ? 49ah nco1accu 51ah ?59ah ? 61ah pwm4dcl 69ah ?71ah ?79ah ? 41bh ? 49bh nco1incl 51bh ?59bh ? 61bh pwm4dch 69bh ?71bh ?79bh ? 41ch ? 49ch nco1inch 51ch ? 59ch ? 61ch pwm4con 69ch ? 71ch ? 79ch ? 41dh ? 49dh ? 51dh ? 59dh ? 61dh ? 69dh ? 71dh ? 79dh ? 41eh ? 49eh nco1con 51eh ?59eh ?61eh ?69eh ?71eh ?79eh ? 41fh ? 49fh nco1clk 51fh ?59fh ?61fh ?69fh ?71fh ?79fh ? 420h unimplemented read as ? 0 ? 4a0h unimplemented read as ? 0 ? 520h unimplemented read as ? 0 ? 5a0h unimplemented read as ? 0 ? 620h unimplemented read as ? 0 ? 6a0h unimplemented read as ? 0 ? 720h unimplemented read as ? 0 ? 7a0h unimplemented read as ? 0 ? 46fh 4efh 56fh 5efh 66fh 6efh 76fh 7efh 470h accesses 70h ? 7fh 4f0h accesses 70h ? 7fh 570h accesses 70h ? 7fh 5f0h accesses 70h ? 7fh 670h accesses 70h ? 7fh 6f0h accesses 70h ? 7fh 770h accesses 70h ? 7fh 7f0h accesses 70h ? 7fh 47fh 4ffh 57fh 5ffh 67fh 6ffh 77fh 7ffh bank 16 bank 17 bank 18 bank 19 bank 20 bank 21 bank 22 bank 23 800h 80bh core registers ( ta b l e 3 - 2 ) 880h 88bh core registers ( ta b l e 3 - 2 ) 900h 90bh core registers ( table 3-2 ) 980h 98bh core registers ( table 3-2 ) a00h a0bh core registers ( table 3-2 ) a80h a8bh core registers ( table 3-2 ) b00h b0bh core registers ( table 3-2 ) b80h b8bh core registers ( table 3-2 ) 80ch unimplemented read as ? 0 ? 88ch unimplemented read as ? 0 ? 90ch unimplemented read as ? 0 ? 98ch unimplemented read as ? 0 ? a0ch unimplemented read as ? 0 ? a8ch unimplemented read as ? 0 ? b0ch unimplemented read as ? 0 ? b8ch unimplemented read as ? 0 ? 86fh 8efh 96fh 9efh a6fh aefh b6fh befh 870h accesses 70h ? 7fh 8f0h accesses 70h ? 7fh 970h accesses 70h ? 7fh 9f0h accesses 70h ? 7fh a70h accesses 70h ? 7fh af0h accesses 70h ? 7fh b70h accesses 70h ? 7fh bf0h accesses 70h ? 7fh 87fh 8ffh 97fh 9ffh a7fh affh b7fh bffh legend: = unimplemented data memory locations, read as ? 0 ?.
pic16(l)f1508/9 ds40001609b-page 24 ? 2011-2013 microchip technology inc. table 3-6: pic16(l)f1508/9 memory map, bank 24-31 legend: = unimplemented data memory locations, read as ? 0 ?. bank 24 bank 25 bank 26 bank 27 bank 28 bank 29 bank 30 bank 31 c00h c0bh core registers ( ta b l e 3 - 2 ) c80h c8bh core registers ( ta b l e 3 - 2 ) d00h d0bh core registers ( ta b l e 3 - 2 ) d80h d8bh core registers ( ta b l e 3 - 2 ) e00h e0bh core registers ( ta b l e 3 - 2 ) e80h e8bh core registers ( ta b l e 3 - 2 ) f00h f0bh core registers ( ta b l e 3 - 2 ) f80h f8bh core registers ( ta b l e 3 - 2 ) c0ch ?c8ch ?d0ch ?d8ch ?e0ch ?e8ch ?f0ch see ta b l e 3 - 7 for register mapping details f8ch see ta b l e 3 - 7 for register mapping details c0dh ?c8dh ?d0dh ?d8dh ?e0dh ?e8dh ? f0dh f8dh c0eh ?c8eh ?d0eh ?d8eh ?e0eh ?e8eh ? f0eh f8eh c0fh ?c8fh ?d0fh ?d8fh ?e0fh ?e8fh ? f0fh f8fh c10h ?c90h ?d10h ?d90h ?e10h ?e90h ? f10h f90h c11h ?c91h ?d11h ?d91h ?e11h ?e91h ? f11h f91h c12h ?c92h ?d12h ?d92h ?e12h ?e92h ? f12h f92h c13h ?c93h ?d13h ?d93h ?e13h ?e93h ? f13h f93h c14h ?c94h ?d14h ?d94h ?e14h ?e94h ? f14h f94h c15h ?c95h ?d15h ?d95h ?e15h ?e95h ? f15h f95h c16h ?c96h ?d16h ?d96h ?e16h ?e96h ? f16h f96h c17h ?c97h ?d17h ?d97h ?e17h ?e97h ? f17h f97h c18h ?c98h ?d18h ?d98h ?e18h ?e98h ? f18h f98h c19h ?c99h ?d19h ?d99h ?e19h ?e99h ? f19h f99h c1ah ?c9ah ?d1ah ?d9ah ?e1ah ?e9ah ? f1ah f9ah c1bh ?c9bh ?d1bh ?d9bh ?e1bh ?e9bh ? f1bh f9bh c1ch ?c9ch ?d1ch ?d9ch ?e1ch ?e9ch ? f1ch f9ch c1dh ?c9dh ?d1dh ?d9dh ?e1dh ?e9dh ? f1dh f9dh c1eh ?c9eh ?d1eh ?d9eh ?e1eh ?e9eh ? f1eh f9eh c1fh ?c9fh ?d1fh ?d9fh ?e1fh ?e9fh ? f1fh f9fh c20h unimplemented read as ? 0 ? ca0h unimplemented read as ? 0 ? d20h unimplemented read as ? 0 ? da0h unimplemented read as ? 0 ? e20h unimplemented read as ? 0 ? ea0h unimplemented read as ? 0 ? f20h fa0h c6fh cefh d6fh defh e6fh eefh f6fh fefh c70h accesses 70h ? 7fh cf0h accesses 70h ? 7fh d70h accesses 70h ? 7fh df0h accesses 70h ? 7fh e70h accesses 70h ? 7fh ef0h accesses 70h ? 7fh f70h accesses 70h ? 7fh ff0h accesses 70h ? 7fh cffh cffh d7fh dffh e7fh effh f7fh fffh
? 2011-2013 microchip technology inc. ds40001609b-page 25 pic16(l)f1508/9 table 3-7: pic16(l)f1508/9 memory map, bank 30-31 bank 30 f0ch ? f0dh ? f0eh ? f0fh clcdata f10h clc1con f11h clc1pol f12h clc1sel0 f13h clc1sel1 f14h clc1gls0 f15h clc1gls1 f16h clc1gls2 f17h clc1gls3 f18h clc2con f19h clc2pol f1ah clc2sel0 f1bh clc2sel1 f1ch clc2gls0 f1dh clc2gls1 f1eh clc2gls2 f1fh clc2gls3 f20h clc3con f21h clc3pol f22h clc3sel0 f23h clc3sel1 f24h clc3gls0 f25h clc3gls1 f26h clc3gls2 f27h clc3gls3 f28h clc4con f29h clc4pol f2ah clc4sel0 f2bh clc4sel1 f2ch clc4gls0 f2dh clc4gls1 f2eh clc4gls2 f2fh clc4gls3 f30h unimplemented read as ? 0 ? f6fh bank 31 f8ch fe3h unimplemented read as ? 0 ? fe4h status_shad fe5h wreg_shad fe6h bsr_shad fe7h pclath_shad fe8h fsr0l_shad fe9h fsr0h_shad feah fsr1l_shad febh fsr1h_shad fech ? fedh stkptr feeh tosl fefh tosh legend: = unimplemented data memory locations, read as ? 0 ?.
pic16(l)f1508/9 ds40001609b-page 26 ? 2011-2013 microchip technology inc. 3.2.6 core function registers summary the core function registers listed in ta bl e 3 - 8 can be addressed from any bank. table 3-8: core funct ion registers summary addr name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0-31 x00h or x80h indf0 addressing this location uses contents of fsr0h/fsr0l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x01h or x81h indf1 addressing this location uses contents of fsr1h/fsr1l to address data memory (not a physical register) xxxx xxxx uuuu uuuu x02h or x82h pcl program counter (pc) least significant byte 0000 0000 0000 0000 x03h or x83h status ? ? ?to pd zdcc ---1 1000 ---q quuu x04h or x84h fsr0l indirect data memory address 0 low pointer 0000 0000 uuuu uuuu x05h or x85h fsr0h indirect data memory address 0 high pointer 0000 0000 0000 0000 x06h or x86h fsr1l indirect data memory address 1 low pointer 0000 0000 uuuu uuuu x07h or x87h fsr1h indirect data memory address 1 high pointer 0000 0000 0000 0000 x08h or x88h bsr ? ? ?bsr<4:0> ---0 0000 ---0 0000 x09h or x89h wreg working register 0000 0000 uuuu uuuu x0ah or x8ah pclath ? write buffer for the upper 7 bits of the program counter -000 0000 -000 0000 x0bh or x8bh intcon gie peie tmr0ie inte iocie tmr0if intf iocif 0000 0000 0000 0000 legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ? 0 ?, r = reserved. shaded locations are unimplemented, read as ? 0 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 27 pic16(l)f1508/9 table 3-9: special function register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets bank 0 00ch porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 --xx xxxx --xx xxxx 00dh portb rb7 rb6 rb5 rb4 ? ? ? ? xxxx ---- xxxx ---- 00eh portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 xxxx xxxx xxxx xxxx 00fh ? unimplemented ? ? 010h ? unimplemented ? ? 011h pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 0000 0-00 0000 0-00 012h pir2 osfif c2if c1if ? bcl1if nco1if ? ? 000- -0-- 000- -0-- 013h pir3 ? ? ? ? clc4if clc3if clc2if clc1if ---- 0000 ---- 0000 014h ? unimplemented ? ? 015h tmr0 holding register for the 8-bit timer0 count xxxx xxxx uuuu uuuu 016h tmr1l holding register for the least significant byte of the 16-bit tmr1 count xxxx xxxx uuuu uuuu 017h tmr1h holding register for the most significant byte of the 16-bit tmr1 count xxxx xxxx uuuu uuuu 018h t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 0000 00-0 uuuu uu-u 019h t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 0000 0x00 uuuu uxuu 01ah tmr2 timer2 module register 0000 0000 0000 0000 01bh pr2 timer2 period register 1111 1111 1111 1111 01ch t2con ? t2outps<3:0> tmr2on t2ckps<1:0> -000 0000 -000 0000 01dh ? unimplemented ? ? 01eh ? unimplemented ? ? 01fh ? unimplemented ? ? bank 1 08ch trisa ? ? trisa5 trisa4 ? (2) trisa2 trisa1 trisa0 --11 1111 --11 1111 08dh trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 1111 ---- 1111 ---- 08eh trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 1111 1111 1111 1111 08fh ? unimplemented ? ? 090h ? unimplemented ? ? 091h pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 0000 0-00 0000 0-00 092h pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 000- 00-- 000- 00-- 093h pie3 ? ? ? ? clc4ie clc3ie clc2ie clc1ie ---- 0000 ---- 0000 094h ? unimplemented ? ? 095h option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 1111 1111 1111 1111 096h pcon stkovf stkunf ?rwdt rmclr ri por bor 00-1 11qq qq-q qquu 097h wdtcon ? ? wdtps<4:0> swdten --01 0110 --01 0110 098h ? unimplemented ? ? 099h osccon ? ircf<3:0> ?scs<1:0> -011 1-00 -011 1-00 09ah oscstat soscr ?ostshfiofr ? ? lfiofr hfiofs 0-q0 --00 q-qq --qq 09bh adresl adc result register low xxxx xxxx uuuu uuuu 09ch adresh adc result register high xxxx xxxx uuuu uuuu 09dh adcon0 ? chs<4:0> go/done adon -000 0000 -000 0000 09eh adcon1 adfm adcs<2:0> ? ? adpref<1:0> 0000 --00 0000 --00 09fh adcon2 trigsel<3:0> ? ? ? ? 0000 ---- 0000 ---- legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 28 ? 2011-2013 microchip technology inc. bank 2 10ch lata ? ?lata5lata4 ? lata2 lata1 lata0 --xx -xxx --uu -uuu 10dh latb latb7 latb6 latb5 latb4 ? ? ? ? xxxx ---- uuuu ---- 10eh latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 xxxx xxxx uuuu uuuu 10fh ? unimplemented ? ? 110h ? unimplemented ? ? 111h cm1con0 c1on c1out c1oe c1pol ? c1sp c1hys c1sync 0000 -100 0000 -100 112h cm1con1 c1intp c1intn c1pch<1:0> ? c1nch<2:0> 0000 -000 0000 -000 113h cm2con0 c2on c2out c2oe c2pol ? c2sp c2hys c2sync 0000 -100 0000 -100 114h cm2con1 c2intp c2intn c2pch<1:0> ? c2nch<2:0> 0000 -000 0000 -000 115h cmout ? ? ? ? ? ?mc2out mc1out ---- --00 ---- --00 116h borcon sboren borfs ? ? ? ? ? borrdy 10-- ---q uu-- ---u 117h fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 0q00 0000 0q00 0000 118h dac1con0 dacen ? dacoe1 dacoe2 ? dacpss ? ? 0-00 -0-- 0-00 -0-- 119h dac1con1 ? ? ? dacr<4:0> ---0 0000 ---0 0000 11ah to 11ch ? unimplemented ? ? 11dh apfcon ? ? ? sssel t1gsel ? clc1sel nco1sel ---0 0-00 ---0 0-00 11eh ? unimplemented ? ? 11fh ? unimplemented ? ? bank 3 18ch ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 ---1 -111 ---1 -111 18dh anselb ? ? ansb5 ansb4 ? ? ? ? --11 ---- --11 ---- 18eh anselc ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 11-- 1111 11-- 1111 18fh ? unimplemented ? ? 190h ? unimplemented ? ? 191h pmadrl flash program memory address register low byte 0000 0000 0000 0000 192h pmadrh ? (2) flash program memory address register high byte 1000 0000 1000 0000 193h pmdatl flash program memory read data register low byte xxxx xxxx uuuu uuuu 194h pmdath ? ? flash program memory read data register high byte --xx xxxx --uu uuuu 195h pmcon1 ? (2) cfgs lwlo free wrerr wren wr rd 1000 x000 1000 q000 196h pmcon2 flash program memory control register 2 0000 0000 0000 0000 197h vregcon (1) ??????vregpm reserved ---- --01 ---- --01 198h ? unimplemented ? ? 199h rcreg usart receive data register 0000 0000 0000 0000 19ah txreg usart transmit data register 0000 0000 0000 0000 19bh spbrgl baud rate generator data register low 0000 0000 0000 0000 19ch spbrgh baud rate generator data register high 0000 0000 0000 0000 19dh rcsta spen rx9 sren cren adden ferr oerr rx9d 0000 000x 0000 000x 19eh txsta csrc tx9 txen sync sendb brgh trmt tx9d 0000 0010 0000 0010 19fh baudcon abdovf rcidl ? sckp brg16 ? wue abden 01-0 0-00 01-0 0-00 table 3-9: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 29 pic16(l)f1508/9 bank 4 20ch wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 --11 1111 --11 1111 20dh wpub wpub7 wpub6 wpub5 wpub4 ? ? ? ? 1111 ---- 1111 ---- 20eh to 210h ? unimplemented ? ? 211h ssp1buf synchronous serial port receive buffer/transmit register xxxx xxxx uuuu uuuu 212h ssp1add add<7:0> 0000 0000 0000 0000 213h ssp1msk msk<7:0> 1111 1111 1111 1111 214h ssp1stat smp cke d/a psr/w ua bf 0000 0000 0000 0000 215h ssp1con1 wcol sspov sspen ckp sspm<3:0> 0000 0000 0000 0000 216h ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 0000 0000 0000 0000 217h ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 0000 0000 0000 0000 218h to 21fh ? unimplemented ? ? bank 5 28ch to 29fh ? unimplemented ? ? bank 6 30ch to 31fh ? unimplemented ? ? bank 7 38ch to 390h ? unimplemented ? ? 391h iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 --00 0000 --00 0000 392h iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 --00 0000 --00 0000 393h iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 --00 0000 --00 0000 394h iocbp iocbp7 iocbp6 iocbp5 iocbp4 ? ? ? ? 0000 ---- 0000 ---- 395h iocbn iocbn7 iocbn6 iocbn5 iocbn4 ? ? ? ? 0000 ---- 0000 ---- 396h iocbf iocbf7 iocbf6 iocbf5 iocbf4 ? ? ? ? 0000 ---- 0000 ---- 397h to 39fh ? unimplemented ? ? bank 8 40ch to 41fh ? unimplemented ? ? bank 9 48ch to 497h ? unimplemented ? ? 498h nco1accl nco1acc<7:0> 0000 0000 0000 0000 499h nco1acch nco1acc<15:8> 0000 0000 0000 0000 49ah nco1accu nco1acc<19:16> 0000 0000 0000 0000 49bh nco1incl nco1inc<7:0> 0000 0000 0000 0000 49ch nco1inch nco1inc<15:8> 0000 0000 0000 0000 49dh ? unimplemented ? ? 49eh nco1con n1en n1oe n1out n1pol ? ? ?n1pfm 0000 ---0 0000 ---0 49fh nco1clk n1pws<2:0> ? ? ?n1cks<1:0> 0000 --00 0000 --00 table 3-9: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 30 ? 2011-2013 microchip technology inc. bank 10 50ch to 51fh ? unimplemented ? ? bank 11 58ch to 59fh ? unimplemented ? ? bank 12 60ch to 610h ? unimplemented ? ? 611h pwm1dcl pwm1dcl<7:6> ? ? ? ? ? ? 00-- ---- 00-- ---- 612h pwm1dch pwm1dch<7:0> xxxx xxxx uuuu uuuu 613h pwm1con0 pwm1en pwm1oe pwm1out pwm1pol ? ? ? ? 0000 ---- 0000 ---- 614h pwm2dcl pwm2dcl<7:6> ? ? ? ? ? ? 00-- ---- 00-- ---- 615h pwm2dch pwm2dch<7:0> xxxx xxxx uuuu uuuu 616h pwm2con0 pwm2en pwm2oe pwm2out pwm2pol ? ? ? ? 0000 ---- 0000 ---- 617h pwm3dcl pwm3dcl<7:6> ? ? ? ? ? ? 00-- ---- 00-- ---- 618h pwm3dch pwm3dch<7:0> xxxx xxxx uuuu uuuu 619h pwm3con0 pwm3en pwm3oe pwm3out pwm3pol ? ? ? ? 0000 ---- 0000 ---- 61ah pwm4dcl pwm4dcl<7:6> ? ? ? ? ? ? 00-- ---- 00-- ---- 61bh pwm4dch pwm4dch<7:0> xxxx xxxx uuuu uuuu 61ch pwm4con0 pwm4en pwm4oe pwm4out pwm4pol ? ? ? ? 0000 ---- 0000 ---- 61dh to 61fh ? unimplemented ? ? bank 13 68ch to 690h ? unimplemented ? ? 691h cwg1dbr ? ?cwg1dbr<5:0> --00 0000 --00 0000 692h cwg1dbf ? ?cwg1dbf<5:0> --xx xxxx --xx xxxx 693h cwg1con0 g1en g1oeb g1oea g1polb g1pola ? ?g1cs0 0000 0--0 0000 0--0 694h cwg1con1 g1asdlb<1:0> g1asdla<1:0> ? g1is<2:0> 0000 -000 0000 -000 695h cwg1con2 g1ase g1arsen ? ? g1asdc2 g1asdc1 g1asdsflt g1asdsclc2 00-- --00 00-- --00 696h to 69fh ? unimplemented ? ? table 3-9: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 31 pic16(l)f1508/9 banks 14-29 x0ch/ x8ch ? x1fh/ x9fh ? unimplemented ? ? bank 30 f0ch to f0eh ? unimplemented ? ? f0fh clcdata ? ? ? ? mlc4out mlc3out mlc2out mlc1out ---- 0000 ---- 0000 f10h clc1con lc1en lc1oe lc1out lc1intp lc1intn lc1mode<2:0> 0000 0000 0000 0000 f11h clc1pol lc1pol ? ? ? lc1g4pol lc1g3pol lc1g2pol lc1g1pol 0--- xxxx 0--- uuuu f12h clc1sel0 ? lc1d2s<2:0> ? lc1d1s<2:0> -xxx -xxx -uuu -uuu f13h clc1sel1 ? lc1d4s<2:0> ? lc1d3s<2:0> -xxx -xxx -uuu -uuu f14h clc1gls0 lc1g1d4t lc1g1d4n lc1g1d3t lc1g1d3n lc1g1d2t lc1g1d2n lc1g1d1t lc1g1d1n xxxx xxxx uuuu uuuu f15h clc1gls1 lc1g2d4t lc1g2d4n lc1g2d3t lc1g2d3n lc1g2d2t lc1g2d2n lc1g2d1t lc1g2d1n xxxx xxxx uuuu uuuu f16h clc1gls2 lc1g3d4t lc1g3d4n lc1g3d3t lc1g3d3n lc1g3d2t lc1g3d2n lc1g3d1t lc1g3d1n xxxx xxxx uuuu uuuu f17h clc1gls3 lc1g4d4t lc1g4d4n lc1g4d3t lc1g4d3n lc1g4d2t lc1g4d2n lc1g4d1t lc1g4d1n xxxx xxxx uuuu uuuu f18h clc2con lc2en lc2oe lc2out lc2intp lc2intn lc2mode<2:0> 0000 0000 0000 0000 f19h clc2pol lc2pol ? ? ? lc2g4pol lc2g3pol lc2g2pol lc2g1pol 0--- xxxx 0--- uuuu f1ah clc2sel0 ? lc2d2s<2:0> ? lc2d1s<2:0> -xxx -xxx -uuu -uuu f1bh clc2sel1 ? lc2d4s<2:0> ? lc2d3s<2:0> -xxx -xxx -uuu -uuu f1ch clc2gls0 lc2g1d4t lc2g1d4n lc2g1d3t lc2g1d3n lc2g1d2t lc2g1d2n lc2g1d1t lc2g1d1n xxxx xxxx uuuu uuuu f1dh clc2gls1 lc2g2d4t lc2g2d4n lc2g2d3t lc2g2d3n lc2g2d2t lc2g2d2n lc2g2d1t lc2g2d1n xxxx xxxx uuuu uuuu f1eh clc2gls2 lc2g3d4t lc2g3d4n lc2g3d3t lc2g3d3n lc2g3d2t lc2g3d2n lc2g3d1t lc2g3d1n xxxx xxxx uuuu uuuu f1fh clc2gls3 lc2g4d4t lc2g4d4n lc2g4d3t lc2g4d3n lc2g4d2t lc2g4d2n lc2g4d1t lc2g4d1n xxxx xxxx uuuu uuuu f20h clc3con lc3en lc3oe lc3out lc3intp lc3intn lc3mode<2:0> 0000 0000 0000 0000 f21h clc3pol lc3pol ? ? ? lc3g4pol lc3g3pol lc3g2pol lc3g1pol 0--- xxxx 0--- uuuu f22h clc3sel0 ? lc3d2s<2:0> ? lc3d1s<2:0> -xxx -xxx -uuu -uuu f23h clc3sel1 ? lc3d4s<2:0> ? lc3d3s<2:0> -xxx -xxx -uuu -uuu f24h clc3gls0 lc3g1d4t lc3g1d4n lc3g1d3t lc3g1d3n lc3g1d2t lc3g1d2n lc3g1d1t lc3g1d1n xxxx xxxx uuuu uuuu f25h clc3gls1 lc3g2d4t lc3g2d4n lc3g2d3t lc3g2d3n lc3g2d2t lc3g2d2n lc3g2d1t lc3g2d1n xxxx xxxx uuuu uuuu f26h clc3gls2 lc3g3d4t lc3g3d4n lc3g3d3t lc3g3d3n lc3g3d2t lc3g3d2n lc3g3d1t lc3g3d1n xxxx xxxx uuuu uuuu f27h clc3gls3 lc3g4d4t lc3g4d4n lc3g4d3t lc3g4d3n lc3g4d2t lc3g4d2n lc3g4d1t lc3g4d1n xxxx xxxx uuuu uuuu f28h clc4con lc4en lc4oe lc4out lc4intp lc4intn lc4mode<2:0> 0000 0000 0000 0000 f29h clc4pol lc4pol ? ? ? lc4g4pol lc4g3pol lc4g2pol lc4g1pol 0--- xxxx 0--- uuuu f2ah clc4sel0 ? lc4d2s<2:0> ? lc4d1s<2:0> -xxx -xxx -uuu -uuu f2bh clc4sel1 ? lc4d4s<2:0> ? lc4d3s<2:0> -xxx -xxx -uuu -uuu f2ch clc4gls0 lc4g1d4t lc4g1d4n lc4g1d3t lc4g1d3n lc4g1d2t lc4g1d2n lc4g1d1t lc4g1d1n xxxx xxxx uuuu uuuu f2dh clc4gls1 lc4g2d4t lc4g2d4n lc4g2d3t lc4g2d3n lc4g2d2t lc4g2d2n lc4g2d1t lc4g2d1n xxxx xxxx uuuu uuuu f2eh clc4gls2 lc4g3d4t lc4g3d4n lc4g3d3t lc4g3d3n lc4g3d2t lc4g3d2n lc4g3d1t lc4g3d1n xxxx xxxx uuuu uuuu f2fh clc4gls3 lc4g4d4t lc4g4d4n lc4g4d3t lc4g4d3n lc4g4d2t lc4g4d2n lc4g4d1t lc4g4d1n xxxx xxxx uuuu uuuu f30h to f6fh ? unimplemented ? ? table 3-9: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 32 ? 2011-2013 microchip technology inc. bank 31 f8ch ? fe3h ? unimplemented ? ? fe4h status_ shad ? ? ? ? ? z_shad dc_shad c_shad ---- -xxx ---- -uuu fe5h wreg_ shad working register shadow xxxx xxxx uuuu uuuu fe6h bsr_ shad ? ? ? bank select register shadow ---x xxxx ---u uuuu fe7h pclath_ shad ? program counter latch high register shadow -xxx xxxx uuuu uuuu fe8h fsr0l_ shad indirect data memory address 0 low pointer shadow xxxx xxxx uuuu uuuu fe9h fsr0h_ shad indirect data memory address 0 high pointer shadow xxxx xxxx uuuu uuuu feah fsr1l_ shad indirect data memory address 1 low pointer shadow xxxx xxxx uuuu uuuu febh fsr1h_ shad indirect data memory address 1 high pointer shadow xxxx xxxx uuuu uuuu fech ? unimplemented ? ? fedh stkptr ? ? ? current stack pointer ---1 1111 ---1 1111 feeh tosl top-of-stack low byte xxxx xxxx uuuu uuuu fefh tosh ? top-of-stack high byte -xxx xxxx -uuu uuuu table 3-9: special function register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 value on por, bor value on all other resets legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved. shaded locations are unimplemented, read as ? 0 ?. note 1: pic16f1508/9 only. 2: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 33 pic16(l)f1508/9 3.3 pcl and pclath the program counter (pc) is 15 bits wide. the low byte comes from the pcl register, which is a readable and writable register. the high byte (pc<14:8>) is not directly readable or writable and comes from pclath. on any reset, the pc is cleared. figure 3-4 shows the five situations for the loading of the pc. figure 3-4: loading of pc in different situations 3.3.1 modifying pcl executing any instruction with the pcl register as the destination simultaneously causes the program counter pc<14:8> bits (pch) to be replaced by the contents of the pclath register. this allows the entire contents of the program counter to be changed by writing the desired upper seven bits to the pclath register. when the lower eight bits are written to the pcl register, all 15 bits of the program counter will change to the values contained in the pclath register and those being written to the pcl register. 3.3.2 computed goto a computed goto is accomplished by adding an offset to the program counter ( addwf pcl ). when performing a table read using a computed goto method, care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). refer to application note an556, ?implementing a table read? (ds00556). 3.3.3 computed function calls a computed function call allows programs to maintain tables of functions and provide another way to execute state machines or look-up tables. when performing a table read using a computed function call , care should be exercised if the table location crosses a pcl memory boundary (each 256-byte block). if using the call instruction, the pch<2:0> and pcl registers are loaded with the operand of the call instruction. pch<6:3> is loaded with pclath<6:3>. the callw instruction enables computed calls by com- bining pclath and w to form the destination address. a computed callw is accomplished by loading the w register with the desired address and executing callw . the pcl register is loaded with the value of w and pch is loaded with pclath. 3.3.4 branching the branching instructions add an offset to the pc. this allows relocatable code and code that crosses page boundaries. there are two forms of branching, brw and bra . the pc will have incremented to fetch the next instruction in both cases. when using either branching instruction, a pcl memory boundary may be crossed. if using brw , load the w register with the desired unsigned address and execute brw . the entire pc will be loaded with the address pc + 1 + w. if using bra , the entire pc will be loaded with pc + 1 +, the signed value of the operand of the bra instruction. pcl pch 0 14 pc pcl pch 0 14 pc alu result 8 7 6 pclath 0 instruction with pcl as destination goto, call opcode <10:0> 11 4 6 pclath 0 pcl pch 0 14 pc w 8 7 6 pclath 0 callw pcl pch 0 14 pc pc + w 15 brw pcl pch 0 14 pc pc + opcode <8:0> 15 bra
pic16(l)f1508/9 ds40001609b-page 34 ? 2011-2013 microchip technology inc. 3.4 stack all devices have a 16-level x 15-bit wide hardware stack (refer to figures 3-5 through 3-8 ). the stack space is not part of either program or data space. the pc is pushed onto the stack when call or callw instructions are executed or an interrupt causes a branch. the stack is poped in the event of a return , retlw or a retfie instruction execution. pclath is not affected by a push or pop operation. the stack operates as a circular buffer if the stvren bit is programmed to ? 0 ? (configuration words). this means that after the stack has been pushed sixteen times, the seventeenth push overwrites the value that was stored from the first push. the eighteenth push overwrites the second push (and so on). the stkovf and stkunf flag bits will be set on an over- flow/underflow, regardless of whether the reset is enabled. 3.4.1 accessing the stack the stack is available through the tosh, tosl and stkptr registers. stkptr is the current value of the stack pointer. tosh:tosl register pair points to the top of the stack. both registers are read/writable. tos is split into tosh and tosl due to the 15-bit size of the pc. to access the stack, adjust the value of stkptr, which will position tosh:tosl, then read/write to tosh:tosl. stkptr is 5 bits to allow detection of overflow and underflow. during normal program operation, call, callw and interrupts will increment stkptr while retlw , return , and retfie will decrement stkptr. at any time stkptr can be inspected to see how much stack is left. the stkptr always points at the currently used place on the stack. therefore, a call or callw will increment the stkptr and then write the pc, and a return will unload the pc and then decrement the stkptr. reference figure 3-5 through figure 3-8 for examples of accessing the stack. figure 3-5: accessing the stack example 1 note 1: there are no instructions/mnemonics called push or pop. these are actions that occur from the execution of the call, callw , return , retlw and retfie instructions or the vectoring to an interrupt address. note: care should be taken when modifying the stkptr while interrupts are enabled. 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 0x00 0x0000 stkptr = 0x1f initial stack configuration: after reset, the stack is empty. the empty stack is initialized so the stack pointer is pointing at 0x1f. if the stack overflow/underflow reset is enabled, the tosh/tosl registers will return ? 0 ?. if the stack overflow/underflow reset is disabled, the tosh/tosl registers will return the contents of stack address 0x0f. 0x1f stkptr = 0x1f stack reset disabled (stvren = 0 ) stack reset enabled (stvren = 1 ) tosh:tosl tosh:tosl
? 2011-2013 microchip technology inc. ds40001609b-page 35 pic16(l)f1508/9 figure 3-6: accessing the stack example 2 figure 3-7: accessing the stack example 3 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x00 this figure shows the stack configuration after the first call or a single interrupt. if a return instruction is executed, the return addre ss will be placed in the program counter and the stack pointer decremented to the empty state (0x1f). tosh:tosl 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 return address 0x06 return address 0x05 return address 0x04 return address 0x03 return address 0x02 return address 0x01 return address 0x00 stkptr = 0x06 after seven call s or six call s and an interrupt, the stack looks like the figure on the left. a series of return instructions will repeatedly place the return addresses into the program counter and pop the stack. tosh:tosl
pic16(l)f1508/9 ds40001609b-page 36 ? 2011-2013 microchip technology inc. figure 3-8: accessing the stack example 4 3.4.2 overflow/underflow reset if the stvren bit in configuration words is programmed to ? 1 ?, the device will be reset if the stack is pushed beyond the sixteenth level or poped beyond the first level, setting the appropriate bits (stkovf or stkunf, respectively) in the pcon register. 3.5 indirect addressing the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the file select registers (fsr). if the fsrn address specifies one of the two indfn registers, the read will return ? 0 ? and the write will not occur (though status bits may be affected). the fsrn register value is created by the pair fsrnh and fsrnl. the fsr registers form a 16-bit address that allows an addressing space with 65536 locations. these locations are divided into three memory regions: ? traditional data memory ? linear data memory ? program flash memory 0x0f 0x0e 0x0d 0x0c 0x0b 0x0a 0x09 0x08 0x07 0x06 0x05 0x04 0x03 0x02 0x01 return address 0x00 stkptr = 0x10 when the stack is full, the next call or an interrupt will set the stack pointer to 0x10. this is identical to address 0x00 so the stack will wrap and overwrite the return address at 0x00. if the stack overflow/underflow reset is enabled, a reset will occur and location 0x00 will not be overwritten. return address return address return address return address return address return address return address return address return address return address return address return address return address return address return address tosh:tosl
? 2011-2013 microchip technology inc. ds40001609b-page 37 pic16(l)f1508/9 figure 3-9: indirect addressing 0x0000 0x0fff traditional fsr address range data memory 0x1000 reserved linear data memory reserved 0x2000 0x29af 0x29b0 0x7fff 0x8000 0xffff 0x0000 0x0fff 0x0000 0x7fff program flash memory note: not all memory regions are completely implemented. consult device memory tables for memory limits. 0x1fff
pic16(l)f1508/9 ds40001609b-page 38 ? 2011-2013 microchip technology inc. 3.5.1 traditional data memory the traditional data memory is a region from fsr address 0x000 to fsr address 0xfff. the addresses correspond to the absolute addresses of all sfr, gpr and common registers. figure 3-10: traditio nal data memory map indirect addressing direct addressing bank select location select 4bsr 6 0 from opcode fsrxl 70 bank select location select 00000 00001 00010 11111 0x00 0x7f bank 0 bank 1 bank 2 bank 31 0 fsrxh 70 0000
? 2011-2013 microchip technology inc. ds40001609b-page 39 pic16(l)f1508/9 3.5.2 linear data memory the linear data memory is the region from fsr address 0x2000 to fsr address 0x29af. this region is a virtual region that points back to the 80-byte blocks of gpr memory in all the banks. unimplemented memory reads as 0x00. use of the linear data memory region allows buffers to be larger than 80 bytes because incrementing the fsr beyond one bank will go directly to the gpr memory of the next bank. the 16 bytes of common memory are not included in the linear data memory region. figure 3-11: linear data memory map 3.5.3 program flash memory to make constant data access easier, the entire program flash memory is mapped to the upper half of the fsr address space. when the msb of fsrnh is set, the lower 15 bits are the address in program memory which will be accessed through indf. only the lower eight bits of each memory location is accessible via indf. writing to the program flash memory cannot be accomplished via the fsr/indf interface. all instructions that access program flash memory via the fsr/indf interface will require one additional instruction cycle to complete. figure 3-12: program flash memory map 7 0 1 7 0 0 location select 0x2000 fsrnh fsrnl 0x020 bank 0 0x06f 0x0a0 bank 1 0x0ef 0x120 bank 2 0x16f 0xf20 bank 30 0xf6f 0x29af 0 7 1 7 0 0 location select 0x8000 fsrnh fsrnl 0x0000 0x7fff 0xffff program flash memory (low 8 bits)
pic16(l)f1508/9 ds40001609b-page 40 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 41 pic16(l)f1508/9 4.0 device configuration device configuration consists of configuration words, code protection and device id. 4.1 configuration words there are several configuration word bits that allow different oscillator and memory protection options. these are implemented as configuration word 1 at 8007h and configuration word 2 at 8008h. note: the debug bit in configuration words is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 42 ? 2011-2013 microchip technology inc. 4.2 register definitions: configuration words register 4-1: config1: configuration word 1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 fcmen (1) ieso (1) clkouten boren<1:0> (2) ? bit 13 bit 8 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 cp (3) mclre pwrte wdte<1:0> fosc<2:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 fcmen: fail-safe clock monitor enable bit 1 = fail-safe clock monitor is enabled (1) 0 = fail-safe clock monitor is disabled bit 12 ieso: internal external switchover bit (1) 1 = internal/external switchover (two-speed start-up) mode is enabled 0 = internal/external switchover mode is disabled bit 11 clkouten : clock out enable bit 1 = clkout function is disabled. i/o function on the clkout pin 0 = clkout function is enabled on the clkout pin bit 10-9 boren<1:0>: brown-out reset enable bits (2) 11 = bor enabled 10 = bor enabled during operation and disabled in sleep 01 = bor controlled by sboren bit of the borcon register 00 = bor disabled bit 8 unimplemented: read as ? 1 ? bit 7 cp : code protection bit (3) 1 = program memory code protection is disabled 0 = program memory code protection is enabled bit 6 mclre: mclr /v pp pin function select bit if lvp bit = 1 : this bit is ignored. if lvp bit = 0 : 1 =mclr /v pp pin function is mclr ; weak pull-up enabled. 0 =mclr /v pp pin function is digital input; mclr internally disabled; weak pull-up under control of wpua3 bit. bit 5 pwrte : power-up timer enable bit 1 = pwrt disabled 0 = pwrt enabled bit 4-3 wdte<1:0>: watchdog timer enable bits 11 = wdt enabled 10 = wdt enabled while running and disabled in sleep 01 = wdt controlled by the swdten bit in the wdtcon register 00 = wdt disabled
? 2011-2013 microchip technology inc. ds40001609b-page 43 pic16(l)f1508/9 bit 2-0 fosc<2:0>: oscillator selection bits 111 = ech:external clock, high-power mode: on clkin pin 110 = ecm: external clock, medium-power mode: on clkin pin 101 = ecl: external clock, low-power mode: on clkin pin 100 = intosc oscillator: i/o function on clkin pin 011 = extrc oscillator: external rc circuit connected to clkin pin 010 = hs oscillator: high-speed crystal/resonator connected between osc1 and osc2 pins 001 = xt oscillator: crystal/resonator connected between osc1 and osc2 pins 000 = lp oscillator: low-power crystal connected between osc1 and osc2 pins note 1: when fscm is enabled, two-speed start-up will be automatically enabled, regardless of the ieso bit value. 2: enabling brown-out reset does not automatically enable power-up timer. 3: once enabled, code-protect can only be disabled by bulk erasing the device. register 4-1: conf ig1: config uration word 1 (continued)
pic16(l)f1508/9 ds40001609b-page 44 ? 2011-2013 microchip technology inc. register 4-2: config2: configuration word 2 r/p-1 r/p-1 r/p-1 r/p-1 r/p-1 u-1 lvp (1) debug (3) lpbor borv (2) stvren ? bit 13 bit 8 u-1u-1u-1u-1u-1u-1r/p-1r/p-1 ? ? ? ? ? ?wrt<1:0> bit 7 bit 0 legend: r = readable bit p = programmable bit u = unimplemented bit, read as ?1? ?0? = bit is cleared ?1? = bit is set -n = value when blank or after bulk erase bit 13 lvp: low-voltage programming enable bit (1) 1 = low-voltage programming enabled 0 = high-voltage on mclr must be used for programming bit 12 debug : in-circuit debugger mode bit (3) 1 = in-circuit debugger disabled, icspclk and icspdat are general purpose i/o pins 0 = in-circuit debugger enabled, icspclk and icspdat are dedicated to the debugger bit 11 lpbor : low-power bor enable bit 1 = low-power brown-out reset is disabled 0 = low-power brown-out reset is enabled bit 10 borv: brown-out reset voltage selection bit (2) 1 = brown-out reset voltage ( vbor ), low trip point selected 0 = brown-out reset voltage ( vbor ), high trip point selected bit 9 stvren: stack overflow/underflow reset enable bit 1 = stack overflow or underflow will cause a reset 0 = stack overflow or underflow will not cause a reset bit 8-2 unimplemented: read as ? 1 ? bit 1-0 wrt<1:0>: flash memory self-write protection bits 4 kw flash memory ( pic16(l)f1508 only) 11 = write protection off 10 = 000h to 1ffh write protected, 200h to fffh may be modified 01 = 000h to 7ffh write protected, 800h to fffh may be modified 00 = 000h to fffh write protected, no addresses may be modified 8 kw flash memory ( pic16(l)f1509 only) 11 = write protection off 10 = 000h to 01ffh write protected, 0200h to 1fffh may be modified 01 = 000h to 0fffh write protected, 1000h to 1fffh may be modified 00 = 000h to 1fffh write protected, no addresses may be modified note 1: the lvp bit cannot be programmed to ? 0 ? when programming mode is entered via lvp. 2: see vbor parameter for specific trip point voltages. 3: the debug bit in configuration words is managed automatically by device development tools including debuggers and programmers. for normal device operation, this bit should be maintained as a ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 45 pic16(l)f1508/9 4.3 code protection code protection allows the device to be protected from unauthorized access. internal access to the program memory is unaffected by any code protection setting. 4.3.1 program memory protection the entire program memory space is protected from external reads and writes by the cp bit in configuration words. when cp = 0 , external reads and writes of program memory are inhibited and a read will return all ? 0 ?s. the cpu can continue to read program memory, regardless of the protection bit settings. writing the program memory is dependent upon the write protection setting. see section 4.4 ?write protection? for more information. 4.4 write protection write protection allows the device to be protected from unintended self-writes. applications, such as bootloader software, can be protected while allowing other regions of the program memory to be modified. the wrt<1:0> bits in configuration words define the size of the program memory block that is protected. 4.5 user id four memory locations (8000h-8003h) are designated as id locations where the user can store checksum or other code identification numbers. these locations are readable and writable during normal execution. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. for more information on checksum calculation, see the ? pic12(l)f1501/pic16(l)f150x memory programming specification ? (ds41573).
pic16(l)f1508/9 ds40001609b-page 46 ? 2011-2013 microchip technology inc. 4.6 device id and revision id the memory location 8006h is where the device id and revision id are stored. the upper nine bits hold the device id. the lower five bits hold the revision id. see section 10.4 ?user id, device id and configuration word access? for more information on accessing these memory locations. development tools, such as device programmers and debuggers, may be used to read the device id and revision id. 4.7 register definitions: device id register 4-3: devid: device id register rrrrrr dev<8:3> bit 13 bit 8 rrrrrrrr dev<2:0> rev<4:0> bit 7 bit 0 legend: r = readable bit ?1? = bit is set ?0? = bit is cleared bit 13-5 dev<8:0>: device id bits bit 4-0 rev<4:0>: revision id bits these bits are used to identify the revision (see table under dev<8:0> above). device devid<13:0> values dev<8:0> rev<4:0> pic16f1508 10 1101 001 x xxxx pic16lf1508 10 1101 111 x xxxx pic16f1509 10 1101 010 x xxxx pic16lf1509 10 1110 000 x xxxx
? 2011-2013 microchip technology inc. ds40001609b-page 47 pic16(l)f1508/9 5.0 oscillator module (with fail-safe clock monitor) 5.1 overview the oscillator module has a wide variety of clock sources and selection features that allow it to be used in a wide range of applications while maximizing perfor- mance and minimizing power consumption. figure 5-1 illustrates a block diagram of the oscillator module. clock sources can be supplied from external oscillators, quartz crystal resonators, ceramic resonators and resistor-capacitor (rc) circuits. in addition, the system clock source can be supplied from one of two internal oscillators, with a choice of speeds selectable via software. additional clock features include: ? selectable system clock source between external or internal sources via software. ? two-speed start-up mode, which minimizes latency between external oscillator start-up and code execution. ? fail-safe clock monitor (fscm) designed to detect a failure of the external clock source (lp, xt, hs, ech, ecm, ecl or extrc modes) and switch automatically to the internal oscillator. ? oscillator start-up timer (ost) ensures stability of crystal oscillator sources ? fast start-up oscillator allows internal circuits to power-up and stabilize before switching to the 16 mhz hfintosc the oscillator module can be configured in one of the following clock modes. 1. ecl ? external clock low-power mode (0 mhz to 0.5 mhz) 2. ecm ? external clock medium-power mode (0.5 mhz to 4 mhz) 3. ech ? external clock high-power mode (4 mhz to 20 mhz) 4. lp ? 32 khz low-power crystal mode. 5. xt ? medium gain crystal or ceramic resonator oscillator mode (up to 4 mhz) 6. hs ? high gain crystal or ceramic resonator mode (4 mhz to 20 mhz) 7. extrc ? external resistor-capacitor 8. intosc ? internal oscillator (31 khz to 16 mhz) clock source modes are selected by the fosc<2:0> bits in the configuration words. the fosc bits determine the type of oscillator that will be used when the device is first powered. the ech, ecm, and ecl clock modes rely on an external logic level signal as the device clock source. the lp, xt, and hs clock modes require an external crystal or resonator to be connected to the device. each mode is optimized for a different frequency range. the extrc clock mode requires an external resistor and capacitor to set the oscillator frequency. the intosc internal oscillator block produces a low and high-frequency clock source, designated lfintosc and hfintosc. (see internal oscillator block, figure 5-1 ). a wide selection of device clock frequencies may be derived from these two clock sources.
pic16(l)f1508/9 ds40001609b-page 48 ? 2011-2013 microchip technology inc. figure 5-1: simplified pic ? mcu clock source block diagram primary oscillator (osc) secondary oscillator (sosc) clkin/ osc1/ sosci/ t1cki clkout/ osc2/ sosco/ t1g start-up control logic 16 mhz oscillator fast start-up oscillator 31 khz oscillator prescaler hfintosc (1) 16 mhz 8 mhz 4 mhz 2 mhz 1 mhz *500 khz *250 khz *125 khz 62.5 khz *31.25 khz *31 khz ircf<3:0> 4 intosc secondary clock (1) primary clock hfintosc lfintosc to cpu and peripherals sleep f osc (1) lfintosc (1) to wdt, pwrt, and other peripherals * available with more than one ircf selection clock control fosc<2:0> scs<1:0> 32 600 khz oscillator frc frc (1) to adc and other peripherals rev. 10-000030a_a1 note 1: see section 5.2.2.4 ?peripheral clock sources? .
? 2011-2013 microchip technology inc. ds40001609b-page 49 pic16(l)f1508/9 5.2 clock source types clock sources can be classified as external, internal or peripheral. external clock sources rely on external circuitry for the clock source to function. examples are: oscillator mod- ules (ech, ecm, ecl modes), quartz crystal resona- tors or ceramic resonators (lp, xt and hs modes) and resistor-capacitor (extrc) mode circuits. internal clock sources are contained within the oscillator module. the internal oscillator block has two internal oscillators that are used to generate the internal system clock sources: the 16 mhz high-frequency internal oscillator (hfintosc) and the 31 khz low-frequency internal oscillator (lfintosc). the peripheral clock source is a nominal 600 khz internal rc oscillator, frc. the frc is traditionally used with the adc module, but is sometimes available to other peripherals. see section 5.2.2.4 ?peripheral clock sources? . the system clock can be selected between external or internal clock sources via the system clock select (scs) bits in the osccon register. see section 5.3 ?clock switching? for additional information. 5.2.1 external clock sources an external clock source can be used as the device system clock by performing one of the following actions: ? program the fosc<2:0> bits in the configuration words to select an external clock source that will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to: - secondary oscillator during run-time, or - an external clock source determined by the value of the fosc bits. see section 5.3 ?clock switching? for more informa- tion. 5.2.1.1 ec mode the external clock (ec) mode allows an externally generated logic level signal to be the system clock source. when operating in this mode, an external clock source is connected to the osc1 input. osc2/clkout is available for general purpose i/o or clkout. figure 5-2 shows the pin connections for ec mode. ec mode has three power modes to select from through the f osc bits in the configuration words: ? ech ? high-power, 4-20 mhz ? ecm ? medium-power, 0.5-4 mhz ? ecl ? low-power, 0-0.5 mhz the oscillator start-up timer (ost) is disabled when ec mode is selected. therefore, there is no delay in operation after a power-on reset (por) or wake-up from sleep. because the pic ? mcu design is fully static, stopping the external clock input will have the effect of halting the device while leaving all data intact. upon restarting the external clock, the device will resume operation as if no time had elapsed. figure 5-2: external clock (ec) mode operation 5.2.1.2 lp, xt, hs modes the lp, xt and hs modes support the use of quartz crystal resonators or ceramic resonators connected to osc1 and osc2 ( figure 5-3 ). the three modes select a low, medium or high gain setting of the internal inverter-amplifier to support various resonator types and speed. lp oscillator mode selects the lowest gain setting of the internal inverter-amplifier. lp mode current consumption is the least of the three modes. this mode is designed to drive only 32.768 khz tuning-fork type crystals (watch crystals). xt oscillator mode selects the intermediate gain setting of the internal inverter-amplifier. xt mode current consumption is the medium of the three modes. this mode is best suited to drive resonators with a medium drive level specification. hs oscillator mode selects the highest gain setting of the internal inverter-amplifier. hs mode current consumption is the highest of the three modes. this mode is best suited for resonators that require a high drive setting. figure 5-3 and figure 5-4 show typical circuits for quartz crystal and ceramic resonators, respectively. osc1/clkin osc2/clkout clock from ext. system pic ? mcu f osc /4 or i/o (1) note 1: output depends upon the clkouten bit of the configuration words.
pic16(l)f1508/9 ds40001609b-page 50 ? 2011-2013 microchip technology inc. figure 5-3: quartz crystal operation (lp, xt or hs mode) figure 5-4: ceramic resonator operation (xt or hs mode) 5.2.1.3 oscillator start-up timer (ost) if the oscillator module is configured for lp, xt or hs modes, the oscillator start-up timer (ost) counts 1024 oscillations from osc1. this occurs following a power-on reset (por) and when the power-up timer (pwrt) has expired (if configured), or a wake-up from sleep. during this time, the program counter does not increment and program execution is suspended, unless either fscm or two-speed start-up are enabled. in this case, code will continue to execute at the selected intosc frequency while the ost is counting. the ost ensures that the oscillator circuit, using a quartz crystal resonator or ceramic resonator, has started and is providing a stable system clock to the oscillator module. in order to minimize latency between external oscillator start-up and code execution, the two-speed clock start-up mode can be selected (see section 5.4 ?two-speed clock start-up mode? ). note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) note 1: a series resistor (r s ) may be required for quartz crystals with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . c1 c2 quartz r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu crystal osc2/clkout note 1: a series resistor (r s ) may be required for ceramic resonators with low drive level. 2: the value of r f varies with the oscillator mode selected (typically between 2 m ? to 10 m ?? . 3: an additional parallel feedback resistor (r p ) may be required for proper ceramic resonator operation. c1 c2 ceramic r s (1) osc1/clkin r f (2) sleep to internal logic pic ? mcu r p (3) resonator osc2/clkout
? 2011-2013 microchip technology inc. ds40001609b-page 51 pic16(l)f1508/9 5.2.1.4 secondary oscillator the secondary oscillator is a separate crystal oscillator that is associated with the timer1 peripheral. it is opti- mized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator can be used as an alternate system clock source and can be selected during run-time using clock switching. refer to section 5.3 ?clock switching? for more information. figure 5-5: quartz crystal operation (secondary oscillator) 5.2.1.5 external rc mode the external resistor-capacitor (extrc) mode supports the use of an external rc circuit. this allows the designer maximum flexibility in frequency choice while keeping costs to a minimum when clock accuracy is not required. the rc circuit connects to osc1. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. figure 5-6 shows the external rc mode connections. figure 5-6: external rc modes the rc oscillator frequency is a function of the supply voltage, the resistor (r ext ) and capacitor (c ext ) values and the operating temperature. other factors affecting the oscillator frequency are: ? threshold voltage variation ? component tolerances ? packaging variations in capacitance the user also needs to take into account variation due to tolerance of the external rc components used. note 1: quartz crystal characteristics vary according to type, package and manufacturer. the user should consult the manufacturer data sheets for specifications and recommended application. 2: always verify oscillator performance over the v dd and temperature range that is expected for the application. 3: for oscillator design assistance, reference the following microchip applications notes: ? an826, ? crystal oscillator basics and crystal selection for rfpic ? and pic ? devices ? (ds00826) ? an849, ? basic pic ? oscillator design ? (ds00849) ? an943, ? practical pic ? oscillator analysis and design ? (ds00943) ? an949, ? making your oscillator work ? (ds00949) ? tb097, ? interfacing a micro crystal ms1v-t1k 32.768 khz tuning fork crystal to a pic16f690/ss ? (ds91097) ? an1288, ? design practices for low-power external oscillators ? (ds01288) c1 c2 32.768 khz sosci to internal logic pic ? mcu crystal sosco quartz osc2/clkout c ext r ext pic ? mcu osc1/clkin f osc /4 or internal clock v dd v ss recommended values: 10 k ? ? r ext ? 100 k ? , <3v 3 k ? ? r ext ? 100 k ? , 3-5v c ext > 20 pf, 2-5v note 1: output depends upon the clkouten bit of the configuration words. i/o (1)
pic16(l)f1508/9 ds40001609b-page 52 ? 2011-2013 microchip technology inc. 5.2.2 internal clock sources the device may be configured to use the internal oscil- lator block as the system clock by performing one of the following actions: ? program the fosc<2:0> bits in configuration words to select the intosc clock source, which will be used as the default system clock upon a device reset. ? write the scs<1:0> bits in the osccon register to switch the system clock source to the internal oscillator during run-time. see section 5.3 ?clock switching? for more information. in intosc mode, osc1/clkin is available for general purpose i/o. osc2/clkout is available for general purpose i/o or clkout. the function of the osc2/clkout pin is determined by the clkouten bit in configuration words. the internal oscillator block has two independent oscillators that provides the internal system clock source. 1. the hfintosc (high-frequency internal oscillator) is factory calibrated and operates at 16 mhz. 2. the lfintosc (low-frequency internal oscillator) operates at 31 khz. 5.2.2.1 hfintosc the high-frequency internal oscillator (hfintosc) is a factory calibrated 16 mhz internal clock source. the output of the hfintosc connects to a postscaler and multiplexer (see figure 5-1 ). the frequency derived from the hfintosc can be selected via software using the ircf<3:0> bits of the osccon register. see section 5.2.2.6 ?internal oscillator clock switch timing? for more information. the hfintosc is enabled by: ? configure the ircf<3:0> bits of the osccon register for the desired hf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. a fast start-up oscillator allows internal circuits to power-up and stabilize before switching to hfintosc. the high-frequency internal oscillator ready bit (hfiofr) of the oscstat register indicates when the hfintosc is running. the high-frequency internal oscillator stable bit (hfiofs) of the oscstat register indicates when the hfintosc is running within 0.5% of its final value. 5.2.2.2 lfintosc the low-frequency internal oscillator (lfintosc) is a 31 khz internal clock source. the output of the lfintosc connects to a multiplexer (see figure 5-1 ). select 31 khz, via software, using the ircf<3:0> bits of the osccon register. see section 5.2.2.6 ?internal oscillator clock switch timing? for more information. the lfintosc is also the frequency for the power-up timer (pwrt), watchdog timer (wdt) and fail-safe clock monitor (fscm). the lfintosc is enabled by selecting 31 khz (ircf<3:0> bits of the osccon register = 000 ) as the system clock source (scs bits of the osccon register = 1x ), or when any of the following are enabled: ? configure the ircf<3:0> bits of the osccon register for the desired lf frequency, and ?fosc<2:0> = 100 , or ? set the system clock source (scs) bits of the osccon register to ? 1x ?. peripherals that use the lfintosc are: ? power-up timer (pwrt) ? watchdog timer (wdt) ? fail-safe clock monitor (fscm) the low-frequency internal oscillator ready bit (lfiofr) of the oscstat register indicates when the lfintosc is running. 5.2.2.3 frc the frc clock is an uncalibrated, nominal 600 khz peripheral clock source. the frc is automatically turned on by the peripherals requesting the frc clock. the frc clock continues to run during sleep.
? 2011-2013 microchip technology inc. ds40001609b-page 53 pic16(l)f1508/9 5.2.2.4 peripheral clock sources the clock sources described in this chapter and the timer?s are available to different peripherals. table 5-1 lists the clocks and timers available for each peripheral. 5.2.2.5 internal oscillator frequency selection the system clock speed can be selected via software using the internal oscillator frequency select bits ircf<3:0> of the osccon register. the postscaled output of the 16 mhz hfintosc and 31 khz lfintosc connect to a multiplexer (see figure 5-1 ). the internal oscillator frequency select bits ircf<3:0> of the osccon register ( register 5-1 ) select the frequency output of the internal oscillators. the ircf<3:0> bits of the osccon register allow duplicate selections for some frequencies. these dupli- cate choices can offer system design trade-offs. lower power consumption can be obtained when changing oscillator sources for a given frequency. faster transi- tion times can be obtained between frequency changes that use the same oscillator source. 5.2.2.6 internal oscillator clock switch timing when switching between the hfintosc and the lfintosc, the new oscillator may already be shut down to save power (see figure 5-7 ). if this is the case, there is a delay after the ircf<3:0> bits of the osccon register are modified before the frequency selection takes place. the oscstat register will reflect the current active status of the hfintosc and lfintosc oscillators. the sequence of a frequency selection is as follows: 1. ircf<3:0> bits of the osccon register are modified. 2. if the new clock is shut down, a clock start-up delay is started. 3. clock switch circuitry waits for a falling edge of the current clock. 4. the current clock is held low and the clock switch circuitry waits for a rising edge in the new clock. 5. the new clock is now active. 6. the oscstat register is updated as required. 7. clock switch is complete. see figure 5-7 for more details. if the internal oscillator speed is switched between two clocks of the same source, there is no start-up delay before the new frequency is selected. clock switching time delays are shown in table 5-3 . start-up delay specifications are located in ta bl e 2 9 -8 , ?oscillator parameters?. table 5-1: peripheral clock sources fosc frc hfintosc lfintosc tmr0 tmr1 tmr2 sosc adc x x clc xxxxxxxx comp x x cwg x x eusart x x mssp x x nco x x pwm x x pwrt x tmr0 x tmr1 x x x tmr2 x wdt x note: following any reset, the ircf<3:0> bits of the osccon register are set to ? 0111 ? and the frequency selection is set to 500 khz. the user can modify the ircf bits to select a different frequency.
pic16(l)f1508/9 ds40001609b-page 54 ? 2011-2013 microchip technology inc. figure 5-7: internal oscillator switch timing hfintosc lfintosc ircf <3:0> system clock hfintosc lfintosc ircf <3:0> system clock ?? 0 ?? 0 ?? 0 ?? 0 2-cycle sync running 2-cycle sync running hfintosc lfintosc (fscm and wdt disabled) hfintosc lfintosc (either fscm or wdt enabled) lfintosc hfintosc ircf <3:0> system clock = 0 ? 0 2-cycle sync running lfintosc hfintosc lfintosc turns off unless wdt or fscm is enabled (2) note 1: see tab l e 5 - 3 , ?oscillator switching delays? for more information. 2: lfintosc will continue to run if a peripheral has selected it as the clock source. see section 5.2.2.4 ?peripheral clock sources? . oscillator delay (1) oscillator delay (1)
? 2011-2013 microchip technology inc. ds40001609b-page 55 pic16(l)f1508/9 5.3 clock switching the system clock source can be switched between external and internal clock sources via software using the system clock select (scs) bits of the osccon register. the following clock sources can be selected using the scs bits: ? default system oscillator determined by fosc bits in configuration words ? secondary oscillator 32 khz crystal ? internal oscillator block (intosc) 5.3.1 system clock select (scs) bits the system clock select (scs) bits of the osccon register selects the system clock source that is used for the cpu and peripherals. ? when the scs bits of the osccon register = 00 , the system clock source is determined by value of the fosc<2:0> bits in the configuration words. ? when the scs bits of the osccon register = 01 , the system clock source is the secondary oscillator. ? when the scs bits of the osccon register = 1x , the system clock source is chosen by the internal oscillator frequency selected by the ircf<3:0> bits of the osccon register. after a reset, the scs bits of the osccon register are always cleared. when switching between clock sources, a delay is required to allow the new clock to stabilize. these oscil- lator delays are shown in table 5-3 . 5.3.2 oscillator start-up timer status (osts) bit the oscillator start-up timer status (osts) bit in the oscstat register has different definitions that are dependent on the fosc bit selection in the configuration word. table 5-2 defines the osts bit value for the fosc selections. the normal function of the osts bit is when fosc<2:0> selects one of the external oscillator modes, hs, xt or lp, while the ost is counting pulses on the osc1 pin from the external oscillator, osts = 0 . when the ost has counted 1024 pulses, the osts bit should be set, osts = 1 , indicating the oscillator is stable and ready to be used. when fail-safe clock monitor and/or two-speed start-up are enabled, (fcmen = 1 and/or ieso = 1 ), the device will operate using the internal oscillator (intosc) selected by the ircf<3:0> bits, whenever osts = 0 . when the ost period expires, (osts = 1 ), the system clock will switch to the external oscillator selected. when fail-safe clock monitor and two-speed start-up are disabled, (fcmen = 0 and ieso = 0 ), the device will be held in reset while osts = 0 . when ost period expires, (osts = 1 ), reset will be released and execution will begin 10 f osc cycles later using the external oscillator selected. for definition of the osts bit with clock sources other than external oscillator modes (hs, xt or lp), see tab l e 5 - 2 . the osts bit does not reflect the status of the secondary oscillator. 5.3.3 secondary oscillator the secondary oscillator is a separate crystal oscillator associated with the timer1 peripheral. it is optimized for timekeeping operations with a 32.768 khz crystal connected between the sosco and sosci device pins. the secondary oscillator is enabled using the t1oscen control bit in the t1con register. see section 19.0 ?timer1 module with gate control? for more information about the timer1 peripheral. 5.3.4 secondary oscillator ready (soscr) bit the user must ensure that the secondary oscillator is ready to be used before it is selected as a system clock source. the secondary oscillator ready (soscr) bit of the oscstat register indicates whether the secondary oscillator is ready to be used. after the soscr bit is set, the scs bits can be configured to select the secondary oscillator. note: any automatic clock switch, which may occur from two-speed start-up or fail-safe clock monitor, does not update the scs bits of the osccon register. the user can monitor the osts bit of the oscstat register to determine the current system clock source. see ta bl e 5 - 2 . table 5-2: osts bit definition fosc<2:0> selection scs<1:0> bits 00 01 1x osts value intosc 000 ech, ecm, ecl, extrc 100 hs, xt, lp normal* 00 * normal function for oscillator modes (osts = 0 ), while ost counting (osts = 1 ), after ost count has expired.
pic16(l)f1508/9 ds40001609b-page 56 ? 2011-2013 microchip technology inc. 5.4 two-speed clock start-up mode two-speed start-up mode provides additional power savings by minimizing the latency between external oscil- lator start-up and code execution. in applications that make heavy use of the sleep mode, two-speed start-up will remove the external oscillator start-up time from the time spent awake and can reduce the overall power con- sumption of the device. this mode allows the application to wake-up from sleep, perform a few instructions using the intosc internal oscillator block as the clock source and go back to sleep without waiting for the external oscillator to become stable. two-speed start-up provides benefits when the oscilla- tor module is configured for lp, xt, or hs modes. the oscillator start-up timer (ost) is enabled for these modes and must count 1024 oscillations before the oscil- lator can be used as the system clock source. if the oscillator module is configured for any mode other than lp, xt or hs mode, then two-speed start-up is disabled. this is because the external clock oscillator does not require any stabilization time after por or an exit from sleep. if the ost count reaches 1024 before the device enters sleep mode, the osts bit of the oscstat register is set and program execution switches to the external oscil- lator. however, the system may never operate from the external oscillator if the time spent awake is very short. 5.4.1 two-speed start-up mode configuration two-speed start-up mode is configured by the following settings: ? ieso (of the configuration words) = 1 ; internal/external switchover bit (two-speed start-up mode enabled). ? scs (of the osccon register) = 00 . ? fosc<2:0> bits in the configuration words configured for lp, xt or hs mode. two-speed start-up mode is entered after: ? power-on reset (por) and, if enabled, after power-up timer (pwrt) has expired, or ? wake-up from sleep. 5.4.2 two-speed start-up sequence 1. wake-up from power-on reset or sleep. 2. instructions begin execution by the internal oscillator at the frequency set in the ircf<3:0> bits of the osccon register. 3. ost enabled to count 1024 clock cycles. 4. ost timed out, wait for falling edge of the internal oscillator. 5. osts is set. 6. system clock held low until the next falling edge of new clock (lp, xt or hs mode). 7. system clock is switched to external clock source. 5.4.3 checking two-speed clock status checking the state of the osts bit of the oscstat register will confirm if the cpu is running from the external clock source, as defined by the fosc<2:0> bits in the configuration words, or the internal oscilla- tor. see table 5-2 . table 5-3: oscillator switching delays note: executing a sleep instruction will abort the oscillator start-up time and will cause the osts bit of the oscstat register to remain clear. note: when fscm is enabled, two-speed start-up will automatically be enabled. switch from switch to oscillator delay any clock source lfintosc 1 cycle of each clock source hfintosc 2 ? s (approx.) ech, ecm, ecl, extrc 2 cycles lp, xt, hs 1024 clock cycles (ost) secondary oscillator 1024 secondary oscillator cycles
? 2011-2013 microchip technology inc. ds40001609b-page 57 pic16(l)f1508/9 figure 5-8: two-speed start-up 0 1 1022 1023 pc + 1 t ost t intosc osc1 osc2 program counter system clock pc - n pc
pic16(l)f1508/9 ds40001609b-page 58 ? 2011-2013 microchip technology inc. 5.5 fail-safe clock monitor the fail-safe clock monitor (fscm) allows the device to continue operating should the external oscillator or external clock fail. if an oscillator mode is selected, the fscm can detect oscillator failure any time after the oscillator start-up timer (ost) has expired. when an external clock mode is selected, the fscm can detect failure as soon as the device is released from reset. fscm is enabled by setting the fcmen bit in the configuration words. the fscm is applicable to external oscillator modes (lp, xt, hs) and external clock modes (ech, ecm, ecl, extrc) and the secondary oscillator (sosc). figure 5-9: fscm block diagram 5.5.1 fail-safe detection the fscm module detects a failed oscillator by monitoring falling clock edges and using lfintosc as a time base. see figure 5-9 . detection of a failed oscillator will take 32 to 96 cycles of the lfintosc. figure 5-10 shows a timing diagram of the fscm module. 5.5.2 fail-safe operation when the external clock fails, the fscm switches the cpu clock to an internal clock source and sets the osfif bit of the pir2 register. the internal clock source is determined by the ircf<3:0> bits in the osccon register. when the osfif bit is set, an interrupt will be generated, if the osfie bit in the pie2 register is enabled. the user?s firmware in the interrupt service routine (isr) can then take steps to mitigate the problems that may arise from the failed clock. the system clock will continue to be sourced from the internal clock source until the fail-safe condition has been cleared, see section 5.5.3 ?fail-safe condition clearing? . 5.5.3 fail-safe condition clearing when a fail-safe condition exists, the user must take the following actions to clear the condition before returning to normal operation with the external source. the next sections describe how to clear the fail-safe condition for specific clock selections (fosc bits) and clock switching modes (scs bit settings). 5.5.3.1 external oscillator with scs<1:0> = 00 when a fail-safe condition occurs with the fosc bits selecting external oscillator (fosc<2:0> = hs, xt, lp) and the clock switch has been selected to run from the fosc selection (scs<1:0> = 00 ), the condition is cleared by performing the following procedure. when scs<1:0> = 00 (running from fosc selection) scs<1:0> = 1x : change the scs bits in the osccon register to select the internal oscillator block. this resets the ost timer and allows it to operate again. osfif = 0 : clear the osfif bit in the pir2 register. scs<1:0> = 00 : change the scs bits in the osccon register to select the fosc configuration word clock selection. this will start the ost. the cpu will continue to operate from the internal oscillator until the ost count is reached. when ost expires, the clock module will switch to the external oscillator and the fail-safe condition will be cleared. if the fail-safe condition still exists, the osfif bit will again be set by hardware. 5.5.3.2 external clock with scs<1:0> = 00 when a fail-safe condition occurs with the fosc bits selecting external clock (fosc<2:0> = ech, ecm, ecl, extrc) and the clock switch has selected to run from the fosc selection (scs<1:0> = 00 ), the condi- tion is cleared by performing the following procedure. when scs<1:0> = 00 (running from fosc selection) scs<1:0> = 1x : change the scs bits in the osccon register to select the internal oscillator block. this resets the ost timer and allows it to operate again. osfif = 0 : clear the osfif bit in the pir2 register. external lfintosc 64 s r q 31 khz (~32 ? s) 488 hz (~2 ms) clock monitor latch clock failure detected oscillator clock q sample clock
? 2011-2013 microchip technology inc. ds40001609b-page 59 pic16(l)f1508/9 scs<1:0> = 00 : change the scs bits in the osccon register to select the fosc configuration word clock selection. since the ost is not applicable with external clocks, the clock module will immediately switch to the external clock, and the fail-safe condition will be cleared. if the fail-safe condition still exists, the osfif bit will again be set by hardware. 5.5.3.3 secondary oscillator with scs<1:0> = 01 when a fail-safe condition occurs with the clock switch selected to run from the secondary oscillator selection (scs<1:0> = 01 ), regardless of the fosc selection, the condition is cleared by performing the following pro- cedure. scs<1:0> = 01 (secondary oscillator) scs<1:0> = 1x : change the scs bits in the osccon register to select the internal oscillator block. osfif = 0 : clear the osfif bit in the pir2 register. read soscr: the ost is not used with the secondary oscillator, therefore, the user must determine if the secondary oscillator is ready by monitoring the soscr bit in the oscstat register. when the soscr bit is set, the secondary oscillator is ready. scs<1:0> = 01 : change the scs bits in the osccon register to select the secondary oscillator. the clock module will immediately switch to the secondary oscillator and the fail-safe condition will be cleared. if the fail-safe condition still exists, the osfif bit will again be set by hardware. 5.5.4 reset or wake-up from sleep the fscm is designed to detect external oscillator or external clock failures. when fscm is used with an external oscillator, the oscillator start-up timer (ost) count must expire before the fscm becomes active. the ost is used after waking up from sleep and after any type of reset. when the fscm is used with external clocks, the ost is not used and the fscm will be active as soon as the reset or wake-up has completed. when the fscm is enabled, the two-speed start-up is also enabled. therefore, the device will always be exe- cuting code while the ost is operating. figure 5-10: fscm timing diagram note: due to the wide range of oscillator start-up times, the fail-safe circuit is not active during oscillator start-up (i.e., after exiting reset or sleep). osfif system clock output sample clock failure detected oscillator failure note: the system clock is normally at a much higher frequency than the sample clock. the relative frequencies in this example have been chosen for clarity. (q) te s t test test clock monitor output
pic16(l)f1508/9 ds40001609b-page 60 ? 2011-2013 microchip technology inc. 5.6 register definitions: oscillator control register 5-1: osccon: os cillator control register u-0 r/w-0/0 r/w-1/1 r/w-1/1 r/w-1/1 u-0 r/w-0/0 r/w-0/0 ? ircf<3:0> ? scs<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 ircf<3:0>: internal oscillator frequency select bits 1111 =16mhz 1110 =8mhz 1101 =4mhz 1100 =2mhz 1011 =1mhz 1010 = 500 khz (1) 1001 = 250 khz (1) 1000 = 125 khz (1) 0111 = 500 khz (default upon reset) 0110 = 250 khz 0101 = 125 khz 0100 = 62.5 khz 001x = 31.25 khz 000x =31khz lf bit 2 unimplemented: read as ? 0 ? bit 1-0 scs<1:0>: system clock select bits 1x = internal oscillator block 01 = secondary oscillator 00 = clock determined by fosc<2:0> in configuration words. note 1: duplicate frequency derived from hfintosc.
? 2011-2013 microchip technology inc. ds40001609b-page 61 pic16(l)f1508/9 register 5-2: oscstat: oscillator status register r-1/q u-0 r-q/q r-0/q u-0 u-0 r-0/q r-0/q soscr ? osts hfiofr ? ? lfiofr hfiofs bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = conditional bit 7 soscr: secondary oscillator ready bit if t1oscen = 1 : 1 = secondary oscillator is ready 0 = secondary oscillator is not ready if t1oscen = 0 : 1 = timer1 clock source is always ready bit 6 unimplemented: read as ? 0 ? bit 5 osts: oscillator start-up timer status bit when the fosc<2:0> bits select hs, xt or lp oscillator : 1 = ost has counted 1024 clocks, device is clocked by the fosc<2:0> bit selection 0 = ost is counting, device is clocked from the internal oscillator (intosc) selected by the ircf<3:0> bits. for all other fosc<2:0> bit selections : see table 5-2 , ?osts bit definition?. bit 4 hfiofr: high-frequency internal oscillator ready bit 1 = hfintosc is ready 0 = hfintosc is not ready bit 3-2 unimplemented: read as ? 0 ? bit 1 lfiofr: low-frequency internal oscillator ready bit 1 = lfintosc is ready 0 = lfintosc is not ready bit 0 hfiofs: high-frequency internal oscillator stable bit 1 = hfintosc 16 mhz oscillator is stable and is driving the intosc 0 = hfintosc 16 mhz is not stable, the start-up oscillator is driving intosc
pic16(l)f1508/9 ds40001609b-page 62 ? 2011-2013 microchip technology inc. table 5-4: summary of registers asso ciated with clock sources table 5-5: summary of configuration word wi th clock sources name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ? ircf<3:0> ?scs<1:0> 60 oscstat soscr ?ostshfiofr ? ? lfiofr hfiofs 61 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ? tmr1on 171 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by clock sources.
? 2011-2013 microchip technology inc. ds40001609b-page 63 pic16(l)f1508/9 6.0 resets there are multiple ways to reset this device: ? power-on reset (por) ? brown-out reset (bor) ? low-power brown-out reset (lpbor) ?mclr reset ?wdt reset ? reset instruction ? stack overflow ? stack underflow ? programming mode exit to a l l o w v dd to stabilize, an optional power-up timer can be enabled to extend the reset time after a bor or por event. a simplified block diagram of the on-chip reset circuit is shown in figure 6-1 . figure 6-1: simplified block di agram of on-chip reset circuit device reset power-on reset wdt time-out brown-out reset lpbor reset reset instruction mclre sleep bor active (1) pwrte lfintosc v dd icsp? programming mode exit stack underflow stack overlfow v pp /mclr rev. 10-000006a_a1 r power-up timer note 1: see table 6-1 for bor active conditions.
pic16(l)f1508/9 ds40001609b-page 64 ? 2011-2013 microchip technology inc. 6.1 power-on reset (por) the por circuit holds the device in reset until v dd has reached an acceptable level for minimum operation. slow rising v dd , fast operating speeds or analog performance may require greater than minimum v dd . the pwrt, bor or mclr features can be used to extend the start-up period until all device operation conditions have been met. 6.1.1 power-up timer (pwrt) the power-up timer provides a nominal 64 ms time-out on por or brown-out reset. the device is held in reset as long as pwrt is active. the pwrt delay allows additional time for the v dd to rise to an acceptable level. the power-up timer is enabled by clearing the pwrte bit in configuration words. the power-up timer starts after the release of the por and bor. for additional information, refer to application note an607, ?power-up trouble shooting? (ds00607). 6.2 brown-out reset (bor) the bor circuit holds the device in reset when v dd reaches a selectable minimum level. between the por and bor, complete voltage range coverage for execution protection can be implemented. the brown-out reset module has four operating modes controlled by the boren<1:0> bits in configu- ration words. the four operating modes are: ? bor is always on ? bor is off when in sleep ? bor is controlled by software ? bor is always off refer to tab le 6 - 1 for more information. the brown-out reset voltage level is selectable by configuring the borv bit in configuration words. a v dd noise rejection filter prevents the bor from trig- gering on small events. if v dd falls below v bor for a duration greater than parameter t bordc , the device will reset. see figure 6-2 for more information. table 6-1: bor operating modes 6.2.1 bor is always on when the boren bits of configuration words are pro- grammed to ? 11 ?, the bor is always on. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is active during sleep. the bor does not delay wake-up from sleep. 6.2.2 bor is off in sleep when the boren bits of configuration words are pro- grammed to ? 10 ?, the bor is on, except in sleep. the device start-up will be delayed until the bor is ready and v dd is higher than the bor threshold. bor protection is not active during sleep. the device wake-up will be delayed until the bor is ready. 6.2.3 bor controlled by software when the boren bits of configuration words are programmed to ? 01 ?, the bor is controlled by the sboren bit of the borcon register. the device start-up is not delayed by the bor ready condition or the v dd level. bor protection begins as soon as the bor circuit is ready. the status of the bor circuit is reflected in the borrdy bit of the borcon register. bor protection is unchanged by sleep. boren<1:0> sboren device mode bor mode instruction execution upon: release of por or wake-up from sleep 11 x x active waits for bor ready (1) (borrdy = 1 ) 10 x awake active waits for bor ready (borrdy = 1 ) sleep disabled 01 1 x active waits for bor ready (1) (borrdy = 1 ) 0 x disabled begins immediately (borrdy = x) 00 x xdisabled note 1: in these specific cases, ?release of por? and ?wake-up from sleep,? there is no delay in start-up. the bor ready flag, (borrdy = 1 ), will be set before the cpu is ready to execute instructions because the bor circuit is forced on by the boren<1:0> bits.
? 2011-2013 microchip technology inc. ds40001609b-page 65 pic16(l)f1508/9 figure 6-2: brown -out situations 6.3 register definitions: bor control register 6-1: borco n: brown-out reset control register r/w-1/u r/w-0/u u-0 u-0 u-0 u-0 u-0 r-q/u sboren borfs ? ? ? ? ?borrdy bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 sboren: software brown-out reset enable bit if boren <1:0> in configuration word s = 01 : 1 = bor enabled 0 = bor disabled if boren <1:0> in configuration word s ? 0 1 : sboren is read/write, but has no effect on the bor bit 6 borfs: brown-out reset fast start bit (1) if boren <1:0> = 10 (disabled in sleep) or boren<1:0> = 01 (under software control): 1 = band gap is forced on always (covers sleep/wake-up/operating cases) 0 = band gap operates normally, and may turn off if boren<1:0> = 11 (always on) or boren<1:0> = 00 (always off) borfs is read/write, but has no effect. bit 5-1 unimplemented: read as ? 0 ? bit 0 borrdy: brown-out reset circuit ready status bit 1 = the brown-out reset circuit is active 0 = the brown-out reset circuit is inactive note 1: boren<1:0> bits are located in configuration words. t pwrt (1) v bor v dd internal reset v bor v dd internal reset t pwrt (1) < t pwrt t pwrt (1) v bor v dd internal reset note 1: t pwrt delay only if pwrte bit is programmed to ? 0 ?.
pic16(l)f1508/9 ds40001609b-page 66 ? 2011-2013 microchip technology inc. 6.4 low-power brown-out reset (lpbor) the low-power brown-out reset (lpbor) operates like the bor to detect low voltage conditions on the v dd pin. when too low of a voltage is detected, the device is held in reset. when this occurs, a register bit (bor) is changed to indicate that a bor reset has occurred. the bor bit in pcon is used for both bor and the lpbor. refer to register 6-2 . the lpbor voltage threshold (v lpbor ) has a wider tolerance than the bor (v bor ), but requires much less current (lpbor current) to operate. the lpbor is intended for use when the bor is configured as dis- abled (boren = 00 ) or disabled in sleep mode (boren = 10 ). refer to figure 6-1 to see how the lpbor interacts with other modules. 6.4.1 enabling lpbor the lpbor is controlled by the lpbor bit of configuration words. when the device is erased, the lpbor module defaults to disabled. 6.5 m clr the mclr is an optional external input that can reset the device. the mclr function is controlled by the mclre bit of configuration words and the lvp bit of configuration words ( table 6-2 ). 6.5.1 mclr enabled when mclr is enabled and the pin is held low, the device is held in reset. the mclr pin is connected to v dd through an internal weak pull-up. the device has a noise filter in the mclr reset path. the filter will detect and ignore small pulses. 6.5.2 mclr disabled when mclr is disabled, the pin functions as a general purpose input and the internal weak pull-up is under software control. see section 11.3 ?porta regis- ters? for more information. 6.6 watchdog timer (wdt) reset the watchdog timer generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the to and pd bits in the status register are changed to indicate the wdt reset. see section 9.0 ?watchdog timer (wdt)? for more information. 6.7 reset instruction a reset instruction will cause a device reset. the ri bit in the pcon register will be set to ? 0 ?. see ta b l e 6 - 4 for default conditions after a reset instruction has occurred. 6.8 stack overflow/underflow reset the device can reset when the stack overflows or underflows. the stkovf or stkunf bits of the pcon register indicate the reset condition. these resets are enabled by setting the stvren bit in configuration words. see section 3.4.2 ?overflow/underflow reset? for more information. 6.9 programming mode exit upon exit of programming mode, the device will behave as if a por had just occurred. 6.10 power-up timer the power-up timer optionally delays device execution after a bor or por event. this timer is typically used to allow v dd to stabilize before allowing the device to start running. the power-up timer is controlled by the pwrte bit of configuration words. 6.11 start-up sequence upon the release of a por or bor, the following must occur before the device will begin executing: 1. power-up timer runs to completion (if enabled). 2. m clr must be released (if enabled). the total time-out will vary based on oscillator configu- ration and power-up timer configuration. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information. the power-up timer runs independently of mclr reset. if mclr is kept low long enough, the power-up timer will expire. upon bringing mclr high, the device will begin execution after 10 f osc cycles (see figure 6-3 ). this is useful for testing purposes or to synchronize more than one device operating in parallel. table 6-2: mclr configuration mclre lvp mclr 00 disabled 10 enabled x1 enabled note: a reset does not drive the mclr pin low.
? 2011-2013 microchip technology inc. ds40001609b-page 67 pic16(l)f1508/9 figure 6-3: reset start-up sequence note 1: code execution begins 10 f osc cycles after the f osc clock is released. external oscillators , pwrten = 1 , ieso = 1 code execution (1) external oscillators , pwrten = 0 , ieso = 1 ext. oscillator osc start-up timer t ost t pwrt t ost v dd internal por internal reset mclr f osc begin execution power-up timer int. oscillator code execution (1) external oscillators , pwrten = 1 , ieso = 0 code execution (1) external oscillators , pwrten = 0 , ieso = 0 ext. oscillator osc start-up timer code execution (1) t ost t pwrt t ost v dd internal por internal reset mclr f osc begin execution power-up timer v dd internal por external clock (ec modes), pwrten = 0 internal reset mclr f osc begin execution ext. clock (ec) power-up timer external clock (ec modes), pwrten = 1 code execution (1) code execution (1) t pwrt int. oscillator code execution (1) internal oscillator, pwrten = 0 internal oscillator, pwrten = 1 code execution (1) t pwrt v dd internal por internal reset mclr f osc begin execution power-up timer rev. 10-000032a_a0
pic16(l)f1508/9 ds40001609b-page 68 ? 2011-2013 microchip technology inc. 6.12 determining the cause of a reset upon any reset, multiple bits in the status and pcon registers are updated to indicate the cause of the reset. ta b l e 6 - 3 and tab le 6 - 4 show the reset conditions of these registers. table 6-3: reset status bits and their significance table 6-4: reset condition for special registers stkovf stkunf rwdt rmclr ri por bor to pd condition 001110x11 power-on reset 001110x0x illegal, to is set on por 001110xx0 illegal, pd is set on por 00u11u011 brown-out reset uu0uuuu0u wdt reset uuuuuuu00 wdt wake-up from sleep uuuuuuu10 interrupt wake-up from sleep uuu0uuuuu mclr reset during normal operation uuu0uuu10 mclr reset during sleep u u u u 0 u u u u reset instruction executed 1uuuuuuuu stack overflow reset (stvren = 1 ) u1uuuuuuu stack underflow reset (stvren = 1 ) condition program counter status register pcon register power-on reset 0000h ---1 1000 00-- 110x mclr reset during normal operation 0000h ---u uuuu uu-- 0uuu mclr reset during sleep 0000h ---1 0uuu uu-- 0uuu wdt reset 0000h ---0 uuuu uu-- uuuu wdt wake-up from sleep pc + 1 ---0 0uuu uu-- uuuu brown-out reset 0000h ---1 1uuu 00-- 11u0 interrupt wake-up from sleep pc + 1 (1) ---1 0uuu uu-- uuuu reset instruction executed 0000h ---u uuuu uu-- u0uu stack overflow reset (stvren = 1 ) 0000h ---u uuuu 1u-- uuuu stack underflow reset (stvren = 1 ) 0000h ---u uuuu u1-- uuuu legend: u = unchanged, x = unknown, - = unimplemented bit, reads as ? 0 ?. note 1: when the wake-up is due to an interrupt and the global interrupt enable bit (gie) is set, the return address is pushed on the stack and pc is loaded with the interrupt vector (0004h) after execution of pc + 1.
? 2011-2013 microchip technology inc. ds40001609b-page 69 pic16(l)f1508/9 6.13 power control (pcon) register the power control (pcon) register contains flag bits to differentiate between a: ? power-on reset (por ) ? brown-out reset (bor ) ? reset instruction reset (ri ) ?mclr reset (rmclr ) ? watchdog timer reset (rwdt ) ? stack underflow reset (stkunf) ? stack overflow reset (stkovf) the pcon register bits are shown in register 6-2 . 6.14 register definitions: power control register 6-2: pcon: power control register r/w/hs-0/q r/w/hs-0/q u-0 r/w/hc-1/q r/w/ hc-1/q r/w/hc-1/q r/w/hc-q/u r/w/hc-q/u stkovf stkunf ? r wdt rmclr ri por bor bit 7 bit 0 legend: hc = bit is cleared by hardware hs = bit is set by hardware r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 stkovf: stack overflow flag bit 1 = a stack overflow occurred 0 = a stack overflow has not occurred or cleared by firmware bit 6 stkunf: stack underflow flag bit 1 = a stack underflow occurred 0 = a stack underflow has not occurred or cleared by firmware bit 5 unimplemented: read as ? 0 ? bit 4 rwdt : watchdog timer reset flag bit 1 = a watchdog timer reset has not occurred or set by firmware 0 = a watchdog timer reset has occurred (cleared by hardware) bit 3 rmclr : mclr reset flag bit 1 = a mclr reset has not occurred or set by firmware 0 = a mclr reset has occurred (cleared by hardware) bit 2 ri : reset instruction flag bit 1 = a reset instruction has not been executed or set by firmware 0 = a reset instruction has been executed (cleared by hardware) bit 1 por : power-on reset status bit 1 = no power-on reset occurred 0 = a power-on reset occurred (must be set in software after a power-on reset occurs) bit 0 bor : brown-out reset status bit 1 = no brown-out reset occurred 0 = a brown-out reset occurred (must be set in software after a power-on reset or brown-out reset occurs)
pic16(l)f1508/9 ds40001609b-page 70 ? 2011-2013 microchip technology inc. table 6-5: summary of registers associated with resets table 6-6: summary of config uration word with resets name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page borcon sboren borfs ? ? ? ? ? borrdy 65 pcon stkovf stkunf ?rwdt rmclr ri por bor 69 status ? ? ?to pd z dc c 19 wdtcon ? ? wdtps<4:0> swdten 91 legend: ? = unimplemented bit, reads as ? 0 ?. shaded cells are not used by resets. note 1: other (non power-up) resets include mclr reset and watchdog timer reset during normal operation. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> config2 13:8 ? ? lvp debug lpbor borv stvren ? 44 7:0 ? ? ? ? ? ? wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by resets.
? 2011-2013 microchip technology inc. ds40001609b-page 71 pic16(l)f1508/9 7.0 interrupts the interrupt feature allows certain events to preempt normal program flow. firmware is used to determine the source of the interrupt and act accordingly. some interrupts can be configured to wake the mcu from sleep mode. this chapter contains the following information for interrupts: ? operation ? interrupt latency ? interrupts during sleep ?int pin ? automatic context saving many peripherals produce interrupts. refer to the corresponding chapters for details. a block diagram of the interrupt logic is shown in figure 7-1 . figure 7-1: interrupt logic tmr0if tmr0ie intf inte iocif iocie interrupt to cpu wake-up (if in sleep mode) gie (tmr1if) pir1<0> pirn<7> peie (tmr1ie) pie1<0> peripheral interrupts pien<7> rev. 10-000010a_a0
pic16(l)f1508/9 ds40001609b-page 72 ? 2011-2013 microchip technology inc. 7.1 operation interrupts are disabled upon any device reset. they are enabled by setting the following bits: ? gie bit of the intcon register ? interrupt enable bit(s) for the specific interrupt event(s) ? peie bit of the intcon register (if the interrupt enable bit of the interrupt event is contained in the pie1, pie2 and pie3 registers) the intcon, pir1, pir2 and pir3 registers record individual interrupts via interrupt flag bits. interrupt flag bits will be set, regardless of the status of the gie, peie and individual interrupt enable bits. the following events happen when an interrupt event occurs while the gie bit is set: ? current prefetched instruction is flushed ? gie bit is cleared ? current program counter (pc) is pushed onto the stack ? critical registers are automatically saved to the shadow registers (see ? section 7.5 ?automatic context saving? .? ) ? pc is loaded with the interrupt vector 0004h the firmware within the interrupt service routine (isr) should determine the source of the interrupt by polling the interrupt flag bits. the interrupt flag bits must be cleared before exiting the isr to avoid repeated interrupts. because the gie bit is cleared, any interrupt that occurs while executing the isr will be recorded through its interrupt flag, but will not cause the processor to redirect to the interrupt vector. the retfie instruction exits the isr by popping the previous address from the stack, restoring the saved context from the shadow registers and setting the gie bit. for additional information on a specific interrupt?s operation, refer to its peripheral chapter. 7.2 interrupt latency interrupt latency is defined as the time from when the interrupt event occurs to the time code execution at the interrupt vector begins. the latency for synchronous interrupts is three or four instruction cycles. for asynchronous interrupts, the latency is three to five instruction cycles, depending on when the interrupt occurs. see figure 7-2 and figure 7-3 for more details. note 1: individual interrupt flag bits are set, regardless of the state of any other enable bits. 2: all interrupts will be ignored while the gie bit is cleared. any interrupt occurring while the gie bit is clear will be serviced when the gie bit is set again.
? 2011-2013 microchip technology inc. ds40001609b-page 73 pic16(l)f1508/9 figure 7-2: interrupt latency q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 fosc clkr pc 0004h 0005h pc inst(0004h) nop gie q1 q2 q3 q4 q1 q2 q3 q4 1-cycle instruction at pc pc inst(0004h) nop 2-cycle instruction at pc fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3-cycle instruction at pc execute interrupt inst(pc) interrupt sampled during q1 inst(pc) pc-1 pc+1 nop pc new pc/ pc+1 0005h pc-1 pc+1/fsr addr 0004h nop interrupt gie interrupt inst(pc) nop nop fsr addr pc+1 pc+2 0004h 0005h pc inst(0004h) nop gie pc pc-1 3-cycle instruction at pc interrupt inst(pc) nop nop nop inst(0005h) execute execute execute
pic16(l)f1508/9 ds40001609b-page 74 ? 2011-2013 microchip technology inc. figure 7-3: int pin interrupt timing q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 q2 q1 q3 q4 f osc clkout int pin intf gie instruction flow pc instruction fetched instruction executed interrupt latency pc pc + 1 pc + 1 0004h 0005h inst (0004h) inst (0005h) forced nop inst (pc) inst (pc + 1) inst (pc ? 1) inst (0004h) forced nop inst (pc) ? note 1: intf flag is sampled here (every q1). 2: asynchronous interrupt latency = 3-5 t cy . synchronous latency = 3-4 t cy , where t cy = instruction cycle time. latency is the same whether inst (pc) is a single cycle or a 2-cycle instruction. 3: for minimum width of int pulse, refer to ac specifications in section 29.0 ?electrical specifications? . 4: intf is enabled to be set any time during the q4-q1 cycles. (1) (2) (3) (4) (1)
? 2011-2013 microchip technology inc. ds40001609b-page 75 pic16(l)f1508/9 7.3 interrupts during sleep some interrupts can be used to wake from sleep. to wake from sleep, the peripheral must be able to operate without the system clock. the interrupt source must have the appropriate interrupt enable bit(s) set prior to entering sleep. on waking from sleep, if the gie bit is also set, the processor will branch to the interrupt vector. otherwise, the processor will continue executing instructions after the sleep instruction. the instruction directly after the sleep instruction will always be executed before branching to the isr. refer to section 8.0 ?power- down mode (sleep)? for more details. 7.4 int pin the int pin can be used to generate an asynchronous edge-triggered interrupt. this interrupt is enabled by setting the inte bit of the intcon register. the intedg bit of the option_reg register determines on which edge the interrupt will occur. when the intedg bit is set, the rising edge will cause the interrupt. when the intedg bit is clear, the falling edge will cause the interrupt. the intf bit of the intcon register will be set when a valid edge appears on the int pin. if the gie and inte bits are also set, the processor will redirect program execution to the interrupt vector. 7.5 automatic context saving upon entering an interrupt, the return pc address is saved on the stack. additionally, the following registers are automatically saved in the shadow registers: ? w register ? status register (except for to and pd ) ? bsr register ? fsr registers ? pclath register upon exiting the interrupt service routine, these regis- ters are automatically restored. any modifications to these registers during the isr will be lost. if modifica- tions to any of these registers are desired, the corre- sponding shadow register should be modified and the value will be restored when exiting the isr. the shadow registers are available in bank 31 and are readable and writable. depending on the user?s appli- cation, other registers may also need to be saved.
pic16(l)f1508/9 ds40001609b-page 76 ? 2011-2013 microchip technology inc. 7.6 register definitions: interrupt control register 7-1: intcon: interrupt control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 gie peie tmr0ie inte iocie tmr0if intf iocif (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 gie: global interrupt enable bit 1 = enables all active interrupts 0 = disables all interrupts bit 6 peie: peripheral interrupt enable bit 1 = enables all active peripheral interrupts 0 = disables all peripheral interrupts bit 5 tmr0ie: timer0 overflow interrupt enable bit 1 = enables the timer0 interrupt 0 = disables the timer0 interrupt bit 4 inte: int external interrupt enable bit 1 = enables the int external interrupt 0 = disables the int external interrupt bit 3 iocie: interrupt-on-change enable bit 1 = enables the interrupt-on-change 0 = disables the interrupt-on-change bit 2 tmr0if: timer0 overflow interrupt flag bit 1 = tmr0 register has overflowed 0 = tmr0 register did not overflow bit 1 intf: int external interrupt flag bit 1 = the int external interrupt occurred 0 = the int external interrupt did not occur bit 0 iocif: interrupt-on-change interrupt flag bit (1) 1 = when at least one of the interrupt-on-change pins changed state 0 = none of the interrupt-on-change pins have changed state note 1: the iocif flag bit is read-only and cleared when all the interrupt-on-change flags in the iocxf register have been cleared by software. note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
? 2011-2013 microchip technology inc. ds40001609b-page 77 pic16(l)f1508/9 register 7-2: pie1: peripheral interrupt enable register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gie: timer1 gate interrupt enable bit 1 = enables the timer1 gate acquisition interrupt 0 = disables the timer1 gate acquisition interrupt bit 6 adie: analog-to-digital converter (adc) interrupt enable bit 1 = enables the adc interrupt 0 = disables the adc interrupt bit 5 rcie: usart receive interrupt enable bit 1 = enables the usart receive interrupt 0 = disables the usart receive interrupt bit 4 txie: usart transmit interrupt enable bit 1 = enables the usart transmit interrupt 0 = disables the usart transmit interrupt bit 3 ssp1ie: synchronous serial port (mssp) interrupt enable bit 1 = enables the mssp interrupt 0 = disables the mssp interrupt bit 2 unimplemented: read as ? 0 ? bit 1 tmr2ie: tmr2 to pr2 match interrupt enable bit 1 = enables the timer2 to pr2 match interrupt 0 = disables the timer2 to pr2 match interrupt bit 0 tmr1ie: timer1 overflow interrupt enable bit 1 = enables the timer1 overflow interrupt 0 = disables the timer1 overflow interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt.
pic16(l)f1508/9 ds40001609b-page 78 ? 2011-2013 microchip technology inc. register 7-3: pie2: peripheral interrupt enable register 2 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 u-0 osfie c2ie c1ie ? bcl1ie nco1ie ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfie: oscillator fail interrupt enable bit 1 = enables the oscillator fail interrupt 0 = disables the oscillator fail interrupt bit 6 c2ie: comparator c2 interrupt enable bit 1 = enables the comparator c2 interrupt 0 = disables the comparator c2 interrupt bit 5 c1ie: comparator c1 interrupt enable bit 1 = enables the comparator c1 interrupt 0 = disables the comparator c1 interrupt bit 4 unimplemented: read as ? 0 ? bit 3 bcl1ie: mssp bus collision interrupt enable bit 1 = enables the mssp bus collision interrupt 0 = disables the mssp bus collision interrupt bit 2 nco1ie: numerically controlled oscillator interrupt enable bit 1 = enables the nco interrupt 0 = disables the nco interrupt bit 1-0 unimplemented: read as ? 0 ? note: bit peie of the intcon register must be set to enable any peripheral interrupt.
? 2011-2013 microchip technology inc. ds40001609b-page 79 pic16(l)f1508/9 register 7-4: pie3: peripheral interrupt enable register 3 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? clc4ie clc3ie clc2ie clc1ie bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 clc4ie: configurable logic block 4 interrupt enable bit 1 = enables the clc 4 interrupt 0 = disables the clc 4 interrupt bit 2 clc3ie: configurable logic block 3 interrupt enable bit 1 = enables the clc 3 interrupt 0 = disables the clc 3 interrupt bit 1 clc2ie: configurable logic block 2 interrupt enable bit 1 = enables the clc 2 interrupt 0 = disables the clc 2 interrupt bit 0 clc1ie: configurable logic block 1 interrupt enable bit 1 = enables the clc 1 interrupt 0 = disables the clc 1 interrupt note: bit peie of the intcon register must be set to enable any peripheral interrupt.
pic16(l)f1508/9 ds40001609b-page 80 ? 2011-2013 microchip technology inc. register 7-5: pir1: peripheral interrupt request register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 tmr1gif: timer1 gate interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 adif: adc interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 rcif: usart receive interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 txif: usart transmit interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 3 ssp1if: synchronous serial port (mssp) interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 unimplemented: read as ? 0 ? bit 1 tmr2if: timer2 to pr2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 tmr1if: timer1 overflow interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
? 2011-2013 microchip technology inc. ds40001609b-page 81 pic16(l)f1508/9 register 7-6: pir2: peripheral interrupt request register 2 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 u-0 osfif c2if c1if ? bcl1if nco1if ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 osfif: oscillator fail interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 6 c2if: numerically controlled oscillator flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 5 c1if: numerically controlled oscillator flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 4 unimplemented: read as ? 0 ? bit 3 bcl1if: mssp bus collision interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 nco1if: numerically controlled oscillator flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1-0 unimplemented: read as ? 0 ? note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
pic16(l)f1508/9 ds40001609b-page 82 ? 2011-2013 microchip technology inc. register 7-7: pir3: peripheral interrupt request register 3 u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? clc4if clc3if clc2if clc1if bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 clc4if: configurable logic block 4 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 2 clc3if: configurable logic block 3 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 1 clc2if: configurable logic block 2 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending bit 0 clc1if: configurable logic block 1 interrupt flag bit 1 = interrupt is pending 0 = interrupt is not pending note: interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global enable bit, gie, of the intcon register. user software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt.
? 2011-2013 microchip technology inc. ds40001609b-page 83 pic16(l)f1508/9 table 7-1: summary of registers associated with interrupts name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 161 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pie3 ? ? ? ? clc4ie clc3ie clc2ie clc1ie 79 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 pir3 ? ? ? ? clc4if clc3if clc2if clc1if 82 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupts.
pic16(l)f1508/9 ds40001609b-page 84 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 85 pic16(l)f1508/9 8.0 power-down mode (sleep) the power-down mode is entered by executing a sleep instruction. upon entering sleep mode, the following conditions exist: 1. wdt will be cleared but keeps running, if enabled for operation during sleep. 2. pd bit of the status register is cleared. 3. to bit of the status register is set. 4. cpu clock is disabled. 5. 31 khz lfintosc is unaffected and peripherals that operate from it may continue operation in sleep. 6. timer1 and peripherals that operate from timer1 continue operation in sleep when the timer1 clock source selected is: ?lfintosc ?t1cki ? timer1 oscillator 7. adc is unaffected, if the dedicated frc oscillator is selected. 8. i/o ports maintain the status they had before sleep was executed (driving high, low or high- impedance). 9. resets other than wdt are not affected by sleep mode. refer to individual chapters for more details on peripheral operation during sleep. to minimize current consumption, the following conditions should be considered: ? i/o pins should not be floating ? external circuitry sinking current from i/o pins ? internal circuitry sourcing current from i/o pins ? current draw from pins with internal weak pull-ups ? modules using 31 khz lfintosc ? cwg, nco and clc modules using hfintosc i/o pins that are high-impedance inputs should be pulled to v dd or v ss externally to avoid switching currents caused by floating inputs. examples of internal circuitry that might be sourcing current include the fvr module. see section 13.0 ?fixed voltage reference (fvr)? for more information on this module. 8.1 wake-up from sleep the device can wake-up from sleep through one of the following events: 1. external reset input on mclr pin, if enabled 2. bor reset, if enabled 3. por reset 4. watchdog timer, if enabled 5. any external interrupt 6. interrupts by peripherals capable of running during sleep (see individual peripheral for more information) the first three events will cause a device reset. the last three events are considered a continuation of pro- gram execution. to determine whether a device reset or wake-up event occurred, refer to section 6.12 ?determining the cause of a reset? . when the sleep instruction is being executed, the next instruction (pc + 1) is prefetched. for the device to wake-up through an interrupt event, the corresponding interrupt enable bit must be enabled. wake-up will occur regardless of the state of the gie bit. if the gie bit is disabled, the device continues execution at the instruction after the sleep instruction. if the gie bit is enabled, the device executes the instruction after the sleep instruction, the device will then call the interrupt service routine. in cases where the execution of the instruction following sleep is not desirable, the user should have a nop after the sleep instruction. the wdt is cleared when the device wakes up from sleep, regardless of the source of wake-up. 8.1.1 wake-up using interrupts when global interrupts are disabled (gie cleared) and any interrupt source has both its interrupt enable bit and interrupt flag bit set, one of the following will occur: ? if the interrupt occurs before the execution of a sleep instruction - sleep instruction will execute as a nop . - wdt and wdt prescaler will not be cleared -to bit of the status register will not be set -pd bit of the status register will not be cleared. ? if the interrupt occurs during or after the execu- tion of a sleep instruction - sleep instruction will be completely executed - device will immediately wake-up from sleep - wdt and wdt prescaler will be cleared -to bit of the status register will be set -pd bit of the status register will be cleared even if the flag bits were checked before executing a sleep instruction, it may be possible for flag bits to become set before the sleep instruction completes. to determine whether a sleep instruction executed, test the pd bit. if the pd bit is set, the sleep instruction was executed as a nop .
pic16(l)f1508/9 ds40001609b-page 86 ? 2011-2013 microchip technology inc. figure 8-1: wake-up from sleep through interrupt 8.2 low-power sleep mode this device contains an internal low dropout (ldo) voltage regulator, which allows the device i/o pins to operate at voltages up to 5.5v while the internal device logic operates at a lower voltage. the ldo and its associated reference circuitry must remain active when the device is in sleep mode. low-power sleep mode allows the user to optimize the operating current in sleep. low-power sleep mode can be selected by setting the vregpm bit of the vregcon register, putting the ldo and reference circuitry in a low-power state whenever the device is in sleep. 8.2.1 sleep current vs. wake-up time in the default operating mode, the ldo and reference circuitry remain in the normal configuration while in sleep. the device is able to exit sleep mode quickly since all circuits remain active. in low-power sleep mode, when waking up from sleep, an extra delay time is required for these circuits to return to the normal con- figuration and stabilize. the low-power sleep mode is beneficial for applica- tions that stay in sleep mode for long periods of time. the normal mode is beneficial for applications that need to wake from sleep quickly and frequently. 8.2.2 peripheral usage in sleep some peripherals that can operate in sleep mode will not operate properly with the low-power sleep mode selected. the ldo will remain in the normal-power mode when those peripherals are enabled. the low- power sleep mode is intended for use with these peripherals: ? brown-out reset (bor) ? watchdog timer (wdt) ? external interrupt pin/interrupt-on-change pins ? timer1 (with external clock source) the complementary waveform generator (cwg), the numerically controlled oscillator (nco) and the con- figurable logic cell (clc) modules can utilize the hfintosc oscillator as either a clock source or as an input source. under certain conditions, when the hfintosc is selected for use with the cwg, nco or clc modules, the hfintosc will remain active during sleep. this will have a direct effect on the sleep mode current. please refer to sections section 24.5 ?operation during sleep? , 25.7 ?operation in sleep? and 26.10 ?operation during sleep? for more information. q1 q2 q3 q4 q1 q2 q3 q4 q1 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 clkin (1) clkout (2) interrupt flag gie bit (intcon reg.) instruction flow pc instruction fetched instruction executed pc pc + 1 pc + 2 inst(pc) = sleep inst(pc - 1) inst(pc + 1) sleep processor in sleep interrupt latency (4) inst(pc + 2) inst(pc + 1) inst(0004h) inst(0005h) inst(0004h) forced nop pc + 2 0004h 0005h forced nop t1 osc (3) pc + 2 note 1: external clock. high, medium, low mode assumed. 2: clkout is shown here for timing reference. 3: t1 osc ; see section 29.0 ?electrical specifications? . 4: gie = 1 assumed. in this case after wake-up, the processor calls the isr at 0004h. if gie = 0 , execution will continue in-line. note: the pic16lf1508/9 does not have a con- figurable low-power sleep mode. pic16lf1508/9 is an unregulated device and is always in the lowest power state when in sleep, with no wake-up time pen- alty. this device has a lower maximum v dd and i/o voltage than the pic16f1508/9. see section 29.0 ?elec- trical specifications? for more informa- tion.
? 2011-2013 microchip technology inc. ds40001609b-page 87 pic16(l)f1508/9 8.3 register definitions: voltage regulator control table 8-1: summary of registers as sociated with power-down mode register 8-1: vregcon: voltag e regulator control register (1) u-0 u-0 u-0 u-0 u-0 u-0 r/w-0/0 r/w-1/1 ? ? ? ? ? ?vregpm reserved bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1 vregpm: voltage regulator power mode selection bit 1 = low-power sleep mode enabled in sleep (2) draws lowest current in sleep, slower wake-up 0 = normal power mode enabled in sleep (2) draws higher current in sleep, faster wake-up bit 0 reserved: read as ? 1 ?. maintain this bit set. note 1: pic16f1508/9 only. 2: see section 29.0 ?electrical specifications? . name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 125 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 125 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 125 iocbf iocbf7 iocbf6 iocbf5 iocbf4 ? ? ? ? 126 iocbn iocbn7 iocbn6 iocbn5 iocbn4 ? ? ? ? 126 iocbp iocbp7 iocbp6 iocbp5 iocbp4 ? ? ? ? 126 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pie3 ? ? ? ? clc4ie clc3ie clc2ie clc1ie 79 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 pir3 ? ? ? ? clc4if clc3if clc2if clc1if 82 status ? ? ?to pd z dc c 19 wdtcon ? ? wdtps<4:0> swdten 91 legend: ? = unimplemented, read as ? 0 ?. shaded cells are not used in power-down mode.
pic16(l)f1508/9 ds40001609b-page 88 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 89 pic16(l)f1508/9 9.0 watchdog timer (wdt) the watchdog timer is a system timer that generates a reset if the firmware does not issue a clrwdt instruction within the time-out period. the watchdog timer is typically used to recover the system from unexpected events. the wdt has the following features: ? independent clock source ? multiple operating modes - wdt is always on - wdt is off when in sleep - wdt is controlled by software - wdt is always off ? configurable time-out period is from 1 ms to 256 seconds (nominal) ? multiple reset conditions ? operation during sleep figure 9-1: watchdog ti mer block diagram lfintosc 23-bit programmable prescaler wdt wdt time-out wdtps<4:0> swdten sleep wdte<1:0> = 11 wdte<1:0> = 01 wdte<1:0> = 10
pic16(l)f1508/9 ds40001609b-page 90 ? 2011-2013 microchip technology inc. 9.1 independent clock source the wdt derives its time base from the 31 khz lfintosc internal oscillator. time intervals in this chapter are based on a nominal interval of 1 ms. see section 29.0 ?electrical specifications? for the lfintosc tolerances. 9.2 wdt operating modes the watchdog timer module has four operating modes controlled by the wdte<1:0> bits in configuration words. see ta b l e 9 - 1 . 9.2.1 wdt is always on when the wdte bits of configuration words are set to ? 11 ?, the wdt is always on. wdt protection is active during sleep. 9.2.2 wdt is off in sleep when the wdte bits of configuration words are set to ? 10 ?, the wdt is on, except in sleep. wdt protection is not active during sleep. 9.2.3 wdt controlled by software when the wdte bits of configuration words are set to ? 01 ?, the wdt is controlled by the swdten bit of the wdtcon register. wdt protection is unchanged by sleep. see table 9-1 for more details. table 9-1: wdt operating modes 9.3 time-out period the wdtps bits of the wdtcon register set the time-out period from 1 ms to 256 seconds (nominal). after a reset, the default time-out period is two seconds. 9.4 clearing the wdt the wdt is cleared when any of the following condi- tions occur: ?any reset ? clrwdt instruction is executed ? device enters sleep ? device wakes up from sleep ? oscillator fail ? wdt is disabled ? oscillator start-up timer (ost) is running see table 9-2 for more information. 9.5 operation during sleep when the device enters sleep, the wdt is cleared. if the wdt is enabled during sleep, the wdt resumes counting. when the device exits sleep, the wdt is cleared again. the wdt remains clear until the ost, if enabled, com- pletes. see section 5.0 ?oscillator module (with fail-safe clock monitor)? for more information on the ost. when a wdt time-out occurs while the device is in sleep, no reset is generated. instead, the device wakes up and resumes operation. the to and pd bits in the status register are changed to indicate the event. the rwdt bit in the pcon register can also be used. see section 3.0 ?memory organization? for more information. wdte<1:0> swdten device mode wdt mode 11 x xactive 10 x awake active sleep disabled 01 1 xactive 0 x disabled 00 x x disabled table 9-2: wdt clearing conditions conditions wdt wdte<1:0> = 00 cleared wdte<1:0> = 01 and swdten = 0 wdte<1:0> = 10 and enter sleep clrwdt command oscillator fail detected exit sleep + system clock = t1osc, extrc, intosc, extclk exit sleep + system clock = xt, hs, lp cleared until the end of ost change intosc divider (ircf bits) unaffected
? 2011-2013 microchip technology inc. ds40001609b-page 91 pic16(l)f1508/9 9.6 register definitions: watchdog control register 9-1: wdtcon: wat chdog timer control register u-0 u-0 r/w-0/0 r/w-1/1 r/w-0/0 r/w-1/1 r/w-1/1 r/w-0/0 ? ? wdtps<4:0> swdten bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-1 wdtps<4:0>: watchdog timer period select bits (1) bit value = prescale rate 11111 = reserved. results in minimum interval (1:32) ? ? ? 10011 = reserved. results in minimum interval (1:32) 10010 = 1:8388608 (2 23 ) (interval 256s nominal) 10001 = 1:4194304 (2 22 ) (interval 128s nominal) 10000 = 1:2097152 (2 21 ) (interval 64s nominal) 01111 = 1:1048576 (2 20 ) (interval 32s nominal) 01110 = 1:524288 (2 19 ) (interval 16s nominal) 01101 = 1:262144 (2 18 ) (interval 8s nominal) 01100 = 1:131072 (2 17 ) (interval 4s nominal) 01011 = 1:65536 (interval 2s nominal) (reset value) 01010 = 1:32768 (interval 1s nominal) 01001 = 1:16384 (interval 512 ms nominal) 01000 = 1:8192 (interval 256 ms nominal) 00111 = 1:4096 (interval 128 ms nominal) 00110 = 1:2048 (interval 64 ms nominal) 00101 = 1:1024 (interval 32 ms nominal) 00100 = 1:512 (interval 16 ms nominal) 00011 = 1:256 (interval 8 ms nominal) 00010 = 1:128 (interval 4 ms nominal) 00001 = 1:64 (interval 2 ms nominal) 00000 = 1:32 (interval 1 ms nominal) bit 0 swdten: software enable/disable for watchdog timer bit if wdte<1:0> = 1x : this bit is ignored. if wdte<1:0> = 01 : 1 = wdt is turned on 0 = wdt is turned off if wdte<1:0> = 00 : this bit is ignored. note 1: times are approximate. wdt time is based on 31 khz lfintosc.
pic16(l)f1508/9 ds40001609b-page 92 ? 2011-2013 microchip technology inc. table 9-3: summary of registers associated with watchdog timer table 9-4: summary of configuration word with watchdog timer name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page osccon ? ircf<3:0> ?scs<1:0> 60 pcon stkovf stkunf ?rwdt rmclr ri por bor 69 status ? ? ?to pd z dc c 19 wdtcon ? ? wdtps<4:0> swdten 91 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by watchdog timer. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by watchdog timer.
? 2011-2013 microchip technology inc. ds40001609b-page 93 pic16(l)f1508/9 10.0 flash program memory control the flash program memory is readable and writable during normal operation over the full v dd range. program memory is indirectly addressed using special function registers (sfrs). the sfrs used to access program memory are: ?pmcon1 ?pmcon2 ?pmdatl ?pmdath ? pmadrl ?pmadrh when accessing the program memory, the pmdath:pmdatl register pair forms a 2-byte word that holds the 14-bit data for read/write, and the pmadrh:pmadrl register pair forms a 2-byte word that holds the 15-bit address of the program memory location being read. the write time is controlled by an on-chip timer. the write/erase voltages are generated by an on-chip charge pump rated to operate over the operating voltage range of the device. the flash program memory can be protected in two ways; by code protection (cp bit in configuration words) and write protection (wrt<1:0> bits in configuration words). code protection (cp = 0 ) (1) , disables access, reading and writing, to the flash program memory via external device programmers. code protection does not affect the self-write and erase functionality. code protection can only be reset by a device programmer performing a bulk erase to the device, clearing all flash program memory, configuration bits and user ids. write protection prohibits self-write and erase to a portion or all of the flash program memory, as defined by the bits wrt<1:0>. write protection does not affect a device programmers ability to read, write or erase the device. 10.1 pmadrl and pmadrh registers the pmadrh:pmadrl register pair can address up to a maximum of 32k words of program memory. when selecting a program address value, the msb of the address is written to the pmadrh register and the lsb is written to the pmadrl register. 10.1.1 pmcon1 and pmcon2 registers pmcon1 is the control register for flash program memory accesses. control bits rd and wr initiate read and write, respectively. these bits cannot be cleared, only set, in software. they are cleared by hardware at completion of the read or write operation. the inability to clear the wr bit in software prevents the accidental, premature termination of a write operation. the wren bit, when set, will allow a write operation to occur. on power-up, the wren bit is clear. the wrerr bit is set when a write operation is interrupted by a reset during normal operation. in these situations, following reset, the user can check the wrerr bit and execute the appropriate error handling routine. the pmcon2 register is a write-only register. attempting to read the pmcon2 register will return all ? 0 ?s. to enable writes to the program memory, a specific pattern (the unlock sequence), must be written to the pmcon2 register. the required unlock sequence prevents inadvertent writes to the program memory write latches and flash program memory. 10.2 flash program memory overview it is important to understand the flash program memory structure for erase and programming operations. flash program memory is arranged in rows. a row consists of a fixed number of 14-bit program memory words. a row is the minimum size that can be erased by user software. after a row has been erased, the user can reprogram all or a portion of this row. data to be written into the program memory row is written to 14-bit wide data write latches. these write latches are not directly accessible to the user, but may be loaded via sequential writes to the pmdath:pmdatl register pair. see table 10-1 for erase row size and the number of write latches for flash program memory. note 1: code protection of the entire flash program memory array is enabled by clearing the cp bit of configuration words. note: if the user wants to modify only a portion of a previously programmed row, then the contents of the entire row must be read and saved in ram prior to the erase. then, new data and retained data can be written into the write latches to reprogram the row of flash program memory. how- ever, any unprogrammed locations can be written without first erasing the row. in this case, it is not necessary to save and rewrite the other previously programmed locations.
pic16(l)f1508/9 ds40001609b-page 94 ? 2011-2013 microchip technology inc. 10.2.1 reading the flash program memory to read a program memory location, the user must: 1. write the desired address to the pmadrh:pmadrl register pair. 2. clear the cfgs bit of the pmcon1 register. 3. then, set control bit rd of the pmcon1 register. once the read control bit is set, the program memory flash controller will use the second instruction cycle to read the data. this causes the second instruction immediately following the ? bsf pmcon1,rd ? instruction to be ignored. the data is available in the very next cycle, in the pmdath:pmdatl register pair; therefore, it can be read as two bytes in the following instructions. pmdath:pmdatl register pair will hold this value until another read or until it is written to by the user. figure 10-1: flash program memory read flowchart table 10-1: flash memory organization by device device row erase (words) write latches (words) pic16(l)f1508 32 32 pic16(l)f1509 note: the two instructions following a program memory read are required to be nop s. this prevents the user from executing a 2-cycle instruction on the next instruction after the rd bit is set. start read operation select program or configuration memory (cfgs) select word address (pmadrh:pmadrl) end read operation instruction fetched ignored nop execution forced instruction fetched ignored nop execution forced initiate read operation (rd = 1 ) data read now in pmdath:pmdatl
? 2011-2013 microchip technology inc. ds40001609b-page 95 pic16(l)f1508/9 figure 10-2: flash program me mory read cycle execution example 10-1: flash program memory read q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 bsf pmcon1,rd executed here instr(pc + 1) executed here pc pc + 1 pmadrh,pmadrl pc+3 pc + 5 flash addr rd bit pmdath,pmdatl pc + 3 pc + 4 instr (pc + 1) instr(pc - 1) executed here instr(pc + 3) executed here instr(pc + 4) executed here flash data pmdath pmdatl register instr (pc) instr (pc + 3) instr (pc + 4) instruction ignored forced nop instr(pc + 2) executed here instruction ignored forced nop * this code block will read 1 word of program * memory at the memory address: prog_addr_hi : prog_addr_lo * data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select bank for pmcon registers movlw prog_addr_lo ; movwf pmadrl ; store lsb of address movlw prog_addr_hi ; movwf pmadrh ; store msb of address bcf pmcon1,cfgs ; do not select configuration space bsf pmcon1,rd ; initiate read nop ; ignored ( figure 10-2 ) nop ; ignored ( figure 10-2 ) movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
pic16(l)f1508/9 ds40001609b-page 96 ? 2011-2013 microchip technology inc. 10.2.2 flash memory unlock sequence the unlock sequence is a mechanism that protects the flash program memory from unintended self-write pro- gramming or erasing. the sequence must be executed and completed without interruption to successfully complete any of the following operations: ?row erase ? load program memory write latches ? write of program memory write latches to program memory ? write of program memory write latches to user ids the unlock sequence consists of the following steps: 1. write 55h to pmcon2 2. write aah to pmcon2 3. set the wr bit in pmcon1 4. nop instruction 5. nop instruction once the wr bit is set, the processor will always force two nop instructions. when an erase row or program row operation is being performed, the processor will stall internal operations (typical 2 ms), until the operation is complete and then resume with the next instruction. when the operation is loading the program memory write latches, the processor will always force the two nop instructions and continue uninterrupted with the next instruction. since the unlock sequence must not be interrupted, global interrupts should be disabled prior to the unlock sequence and re-enabled after the unlock sequence is completed. figure 10-3: flash program memory unlock sequence flowchart write 055h to pmcon2 start unlock sequence write 0aah to pmcon2 initiate write or erase operation (wr = 1 ) instruction fetched ignored nop execution forced end unlock sequence instruction fetched ignored nop execution forced
? 2011-2013 microchip technology inc. ds40001609b-page 97 pic16(l)f1508/9 10.2.3 erasing flash program memory while executing code, program memory can only be erased by rows. to erase a row: 1. load the pmadrh:pmadrl register pair with any address within the row to be erased. 2. clear the cfgs bit of the pmcon1 register. 3. set the free and wren bits of the pmcon1 register. 4. write 55h, then aah, to pmcon2 (flash programming unlock sequence). 5. set control bit wr of the pmcon1 register to begin the erase operation. see example 10-2 . after the ? bsf pmcon1,wr ? instruction, the processor requires two cycles to set up the erase operation. the user must place two nop instructions immediately fol- lowing the wr bit set instruction. the processor will halt internal operations for the typical 2 ms erase time. this is not sleep mode as the clocks and peripherals will continue to run. after the erase cycle, the processor will resume operation with the third instruction after the pmcon1 write instruction. figure 10-4: flash program memory erase flowchart disable interrupts (gie = 0 ) start erase operation select program or configuration memory (cfgs) select row address (pmadrh:pmadrl) select erase operation (free = 1 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end erase operation cpu stalls while erase operation completes (2 ms typical) figure 10-3
pic16(l)f1508/9 ds40001609b-page 98 ? 2011-2013 microchip technology inc. example 10-2: erasing one row of program memory ; this row erase routine assumes the following: ; 1. a valid address within the erase row is loaded in addrh:addrl ; 2. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrl movf addrl,w ; load lower 8 bits of erase address boundary movwf pmadrl movf addrh,w ; load upper 6 bits of erase address boundary movwf pmadrh bcf pmcon1,cfgs ; not configuration space bsf pmcon1,free ; specify an erase operation bsf pmcon1,wren ; enable writes movlw 55h ; start of required sequence to initiate erase movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin erase nop ; nop instructions are forced as processor starts nop ; row erase of program memory. ; ; the processor stalls until the erase process is complete ; after erase processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence
? 2011-2013 microchip technology inc. ds40001609b-page 99 pic16(l)f1508/9 10.2.4 writing to flash program memory program memory is programmed using the following steps: 1. load the address in pmadrh:pmadrl of the row to be programmed. 2. load each write latch with data. 3. initiate a programming operation. 4. repeat steps 1 through 3 until all data is written. before writing to program memory, the word(s) to be written must be erased or previously unwritten. pro- gram memory can only be erased one row at a time. no automatic erase occurs upon the initiation of the write. program memory can be written one or more words at a time. the maximum number of words written at one time is equal to the number of write latches. see figure 10-5 (row writes to program memory with 32 write latches) for more details. the write latches are aligned to the flash row address boundary defined by the upper 10-bits of pmadrh:pmadrl, (pmadrh<6:0>:pmadrl<7:5>) with the lower five bits of pmadrl, (pmadrl<4:0>) determining the write latch being loaded. write opera- tions do not cross these boundaries. at the completion of a program memory write operation, the data in the write latches is reset to contain 0x3fff. the following steps should be completed to load the write latches and program a row of program memory. these steps are divided into two parts. first, each write latch is loaded with data from the pmdath:pmdatl using the unlock sequence with lwlo = 1 . when the last word to be loaded into the write latch is ready, the lwlo bit is cleared and the unlock sequence executed. this initiates the programming operation, writing all the latches into flash program memory. 1. set the wren bit of the pmcon1 register. 2. clear the cfgs bit of the pmcon1 register. 3. set the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 1 ?, the write sequence will only load the write latches and will not initiate the write to flash program memory. 4. load the pmadrh:pmadrl register pair with the address of the location to be written. 5. load the pmdath:pmdatl register pair with the program memory data to be written. 6. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the write latch is now loaded. 7. increment the pmadrh:pmadrl register pair to point to the next location. 8. repeat steps 5 through 7 until all but the last write latch has been loaded. 9. clear the lwlo bit of the pmcon1 register. when the lwlo bit of the pmcon1 register is ? 0 ?, the write sequence will initiate the write to flash program memory. 10. load the pmdath:pmdatl register pair with the program memory data to be written. 11. execute the unlock sequence ( section 10.2.2 ?flash memory unlock sequence? ). the entire program memory latch content is now written to flash program memory. an example of the complete write sequence is shown in example 10-3 . the initial address is loaded into the pmadrh:pmadrl register pair; the data is loaded using indirect addressing. note: the special unlock sequence is required to load a write latch with data or initiate a flash programming operation. if the unlock sequence is interrupted, writing to the latches or program memory will not be initiated. note: the program memory write latches are reset to the blank state (0x3fff) at the completion of every write or erase operation. as a result, it is not necessary to load all the program memory write latches. unloaded latches will remain in the blank state.
pic16(l)f1508/9 ds40001609b-page 100 ? 2011-2013 microchip technology inc. figure 10-5: block writes to flash pr ogram memory with 32 write latches 6 8 14 14 14 write latch #31 1fh 14 14 program memory write latches 14 14 14 pmadrh<6:0>: pmadrl<7:5> flash program memory row row address decode addr write latch #30 1eh write latch #1 01h write latch #0 00h addr addr addr 000h 001fh 001eh 0000h 0001h 001h 003fh 003eh 0020h 0021h 002h 005fh 005eh 0040h 0041h 3feh 7fdfh 7fdeh 7fc0h 7fc1h 3ffh 7fffh 7ffeh 7fe0h 7fe1h 14 pmadrl<4:0> 400h 8009h - 801fh 8000h - 8003h configuration words user id 0 - 3 8007h ? 8008h 8006h device id dev / rev reserved reserved configuration memory cfgs = 0 cfgs = 1 pmadrh pmadrl 7 6 0 7 5 4 0 c4 c3 c2 c1 c0 r9 r8 r7 r6 r5 r4 r3 - r1 r0 r2 5 10 pmdath pmdatl 7 5 0 7 0 - - 8004h ? 8005h rev. 10-000004a_a0
? 2011-2013 microchip technology inc. ds40001609b-page 101 pic16(l)f1508/9 figure 10-6: flash program memory write flowchart disable interrupts (gie = 0 ) start write operation select program or config. memory (cfgs) select row address (pmadrh:pmadrl) select write operation (free = 0 ) enable write/erase operation (wren = 1 ) unlock sequence (figure x-x) disable write/erase operation (wren = 0 ) re-enable interrupts (gie = 1 ) end write operation no delay when writing to program memory latches determine number of words to be written into program or configuration memory. the number of words cannot exceed the number of words per row. (word_cnt) load the value to write (pmdath:pmdatl) update the word counter (word_cnt--) last word to write ? increment address (pmadrh:pmadrl++) unlock sequence (figure x-x) cpu stalls while write operation completes (2 ms typical) load write latches only (lwlo = 1 ) write latches to flash (lwlo = 0 ) no yes figure 10-3 figure 10-3
pic16(l)f1508/9 ds40001609b-page 102 ? 2011-2013 microchip technology inc. example 10-3: writing to flash prog ram memory (32 write latches) ; this write routine assumes the following: ; 1. 64 bytes of data are loaded, starting at the address in data_addr ; 2. each word of data to be written is made up of two adjacent bytes in data_addr, ; stored in little endian format ; 3. a valid starting address (the least significant bits = 00000) is loaded in addrh:addrl ; 4. addrh and addrl are located in shared data memory 0x70 - 0x7f (common ram) ; bcf intcon,gie ; disable ints so required sequences will execute properly banksel pmadrh ; bank 3 movf addrh,w ; load initial address movwf pmadrh ; movf addrl,w ; movwf pmadrl ; movlw low data_addr ; load initial data address movwf fsr0l ; movlw high data_addr ; load initial data address movwf fsr0h ; bcf pmcon1,cfgs ; not configuration space bsf pmcon1,wren ; enable writes bsf pmcon1,lwlo ; only load write latches loop moviw fsr0++ ; load first data byte into lower movwf pmdatl ; moviw fsr0++ ; load second data byte into upper movwf pmdath ; movf pmadrl,w ; check if lower bits of address are '00000' xorlw 0x1f ; check if we're on the last of 32 addresses andlw 0x1f ; btfsc status,z ; exit if last of 32 words, goto start_write ; movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor ; loads program memory write latches nop ; incf pmadrl,f ; still loading latches increment address goto loop ; write next latches start_write bcf pmcon1,lwlo ; no more loading latches - actually start flash program ; memory write movlw 55h ; start of required write sequence: movwf pmcon2 ; write 55h movlw 0aah ; movwf pmcon2 ; write aah bsf pmcon1,wr ; set wr bit to begin write nop ; nop instructions are forced as processor writes ; all the program memory write latches simultaneously nop ; to program memory. ; after nops, the processor ; stalls until the self-write process in complete ; after write processor continues with 3rd instruction bcf pmcon1,wren ; disable writes bsf intcon,gie ; enable interrupts required sequence required sequence
? 2011-2013 microchip technology inc. ds40001609b-page 103 pic16(l)f1508/9 10.3 modifying flash program memory when modifying existing data in a program memory row, and data within that row must be preserved, it must first be read and saved in a ram image. program memory is modified using the following steps: 1. load the starting address of the row to be modified. 2. read the existing data from the row into a ram image. 3. modify the ram image to contain the new data to be written into program memory. 4. load the starting address of the row to be rewritten. 5. erase the program memory row. 6. load the write latches with data from the ram image. 7. initiate a programming operation. figure 10-7: flash program memory modify flowchart start modify operation read operation (figure x.x) erase operation (figure x.x) modify image the words to be modified are changed in the ram image end modify operation write operation use ram image (figure x.x) an image of the entire row read must be stored in ram figure 10-2 figure 10-4 figure 10-5
pic16(l)f1508/9 ds40001609b-page 104 ? 2011-2013 microchip technology inc. 10.4 user id, device id and configuration word access instead of accessing program memory, the user id?s, device id/revision id and configuration words can be accessed when cfgs = 1 in the pmcon1 register. this is the region that would be pointed to by pc<15> = 1 , but not all addresses are accessible. different access may exist for reads and writes. refer to tab le 1 0- 2 . when read access is initiated on an address outside the parameters listed in tab le 1 0- 2 , the pmdath:pmdatl register pair is cleared, reading back ? 0 ?s. table 10-2: user id, device id and configuration word access (cfgs = 1 ) example 10-4: conf iguration word and device id access address function read access write access 8000h-8003h user ids yes yes 8006h device id/revision id yes no 8007h-8008h configuration words 1 and 2 yes no * this code block will read 1 word of program memory at the memory address: * prog_addr_lo (must be 00h-08h) data will be returned in the variables; * prog_data_hi, prog_data_lo banksel pmadrl ; select correct bank movlw prog_addr_lo ; movwf pmadrl ; store lsb of address clrf pmadrh ; clear msb of address bsf pmcon1,cfgs ; select configuration space bcf intcon,gie ; disable interrupts bsf pmcon1,rd ; initiate read nop ; executed (see figure 10-2 ) nop ; ignored (see figure 10-2 ) bsf intcon,gie ; restore interrupts movf pmdatl,w ; get lsb of word movwf prog_data_lo ; store in user location movf pmdath,w ; get msb of word movwf prog_data_hi ; store in user location
? 2011-2013 microchip technology inc. ds40001609b-page 105 pic16(l)f1508/9 10.5 write verify it is considered good programming practice to verify that program memory writes agree with the intended value. since program memory is stored as a full page then the stored program memory contents are compared with the intended data stored in ram after the last write is complete. figure 10-8: flash program memory verify flowchart start verify operation read operation (figure x.x) end verify operation this routine assumes that the last row of data written was from an image saved in ram. this image will be used to verify the data currently stored in flash program memory. pmdat = ram image ? last word ? fail verify operation no yes yes no figure 10-2
pic16(l)f1508/9 ds40001609b-page 106 ? 2011-2013 microchip technology inc. 10.6 register definitions: flash program memory control register 10-1: pmdatl: program memory data low byte register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pmdat<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmdat<7:0> : read/write value for least significant bits of program memory register 10-2: pmdath: program memory data high byte register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? pmdat<13:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 pmdat<13:8> : read/write value for most significant bits of program memory register 10-3: pmadrl: program me mory address low byte register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 pmadr<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pmadr<7:0> : specifies the least significant bits for program memory address register 10-4: pmadrh: program memory address high byte register u-1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? (1) pmadr<14:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 1 ? bit 6-0 pmadr<14:8> : specifies the most significant bits for program memory address note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 107 pic16(l)f1508/9 register 10-5: pmcon1: progra m memory control 1 register u-1 r/w-0/0 r/w-0/0 r/w/hc-0/0 r/w/hc-x/q (2) r/w-0/0 r/s/hc-0/0 r/s/hc-0/0 ? (1) cfgs lwlo free wrerr wren wr rd bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is clear ed hc = bit is cleared by hardware bit 7 unimplemented: read as ? 1 ? bit 6 cfgs: configuration select bit 1 = access configuration, user id and device id registers 0 = access flash program memory bit 5 lwlo: load write latches only bit (3) 1 = only the addressed program memory write latch is loaded/updated on the next wr command 0 = the addressed program memory write latch is loaded/ updated and a write of all program memory write latches will be initiated on the next wr command bit 4 free: program flash erase enable bit 1 = performs an erase operation on the next wr command (hardware cleared upon completion) 0 = performs a write operation on the next wr command bit 3 wrerr: program/erase error flag bit 1 = condition indicates an improper program or erase sequenc e attempt or termination (bit is set automatically on any set attempt (write ? 1 ?) of the wr bit). 0 = the program or erase operation completed normally. bit 2 wren: program/erase enable bit 1 = allows program/erase cycles 0 = inhibits programming/erasing of program flash bit 1 wr: write control bit 1 = initiates a program flash program/erase operation. the operation is self-timed and the bit is cl eared by hardware once operation is complete. the wr bit can only be set (not cleared) in software. 0 = program/erase operation to the flash is complete and inactive. bit 0 rd: read control bit 1 = initiates a program flash read. read takes one cycle . rd is cleared in hardware. the rd bit can only be set (not cleared) in software. 0 = does not initiate a program flash read. note 1: unimplemented bit, read as ? 1 ?. 2: the wrerr bit is automatically set by hardware when a program memory writ e or erase operation is started (wr = 1 ). 3: the lwlo bit is ignored during a program memory erase operation (free = 1 ).
pic16(l)f1508/9 ds40001609b-page 108 ? 2011-2013 microchip technology inc. table 10-3: summary of registers as sociated with flash program memory table 10-4: summary of configuration word with flash program memory register 10-6: pmcon2: progra m memory control 2 register w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 w-0/0 program memory control register 2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? s = bit can only be set x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 flash memory unlock pattern bits to unlock writes, a 55h must be written first, followed by an aah, before setting the wr bit of the pmcon1 register. the value written to this register is used to unlock the writes. there are specific timing requirements on these writes. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pmcon1 ? (1) cfgs lwlo free wrerr wren wr rd 107 pmcon2 program memory control register 2 108 pmadrl pmadrl<7:0> 106 pmadrh ? (1) pmadrh<6:0> 106 pmdatl pmdatl<7:0> 106 pmdath ? ? pmdath<5:0> 106 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> config2 13:8 ? ? lvp debug lpbor borv stvren ? 44 7:0 ? ? ? ? ? ?wrt<1:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by flash program memory.
? 2011-2013 microchip technology inc. ds40001609b-page 109 pic16(l)f1508/9 11.0 i/o ports each port has three standard registers for its operation. these registers are: ? trisx registers (data direction) ? portx registers (reads the levels on the pins of the device) ? latx registers (output latch) some ports may have one or more of the following additional registers. these registers are: ? anselx (analog select) ? wpux (weak pull-up) in general, when a peripheral is enabled on a port pin, that pin cannot be used as a general purpose output. however, the pin can still be read. the data latch (latx registers) is useful for read-modify-write operations on the value that the i/o pins are driving. a write operation to the latx register has the same effect as a write to the corresponding portx register. a read of the latx register reads of the values held in the i/o port latches, while a read of the portx register reads the actual i/o pin value. ports that support analog inputs have an associated anselx register. when an ansel bit is set, the digital input buffer associated with that bit is disabled. disabling the input buffer prevents analog signal levels on the pin between a logic high and low from causing excessive current in the logic input circuitry. a simplified model of a generic i/o port, without the interfaces to other peripherals, is shown in figure 11-1 . figure 11-1: generic i/o port operation table 11-1: port availability per device device porta portb portc pic16(l)f1508/9 q d ck write latx data register i/o pin read portx write portx trisx read latx data bus to digital peripherals anselx v dd v ss to analog peripherals
pic16(l)f1508/9 ds40001609b-page 110 ? 2011-2013 microchip technology inc. 11.1 alternate pin function the alternate pin function control (apfcon) register is used to steer specific peripheral input and output functions between different pins. the apfcon register is shown in register 11-1 . for this device family, the following functions can be moved between different pins. ?ss ?t1g ?clc1 ? nco1 these bits have no effect on the values of any tris register. port and tris overrides will be routed to the correct pin. the unselected pin will be unaffected. 11.2 register definitions: alternate pin function control register 11-1: apfcon: alternat e pin function co ntrol register u-0 u-0 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 ? ? ? sssel t1gsel ? clc1sel nco1sel bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4 sssel: pin selection bit 1 =ss function is on ra3 0 =ss function is on rc6 bit 3 t1gsel: pin selection bit 1 = t1g function is on ra3 0 = t1g function is on ra4 bit 2 unimplemented: read as ? 0 ? bit 1 clc1sel: pin selection bit 1 = clc1 function is on rc5 0 = clc1 function is on ra2 bit 0 nco1sel: pin selection bit 1 = nco1 function is on rc6 0 = nco1 function is on rc1
? 2011-2013 microchip technology inc. ds40001609b-page 111 pic16(l)f1508/9 11.3 porta registers 11.3.1 data register porta is a 6-bit wide, bidirectional port. the corresponding data direction register is trisa ( register 11-3 ). setting a trisa bit (= 1 ) will make the corresponding porta pin an input (i.e., disable the output driver). clearing a trisa bit (= 0 ) will make the corresponding porta pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). the exception is ra3, which is input-only and its tris bit will always read as ? 1 ?. example 11-1 shows how to initialize an i/o port. reading the porta register ( register 11-2 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (lata). 11.3.2 direction control the trisa register ( register 11-3 ) controls the porta pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisa register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.3.3 analog control the ansela register ( register 11-5 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate ansela bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the ansela bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. example 11-1: initializing porta 11.3.4 porta functions and output priorities each porta pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-2 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc and comparator inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below in table 11-2 . note: the ansela bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. banksel porta ; clrf porta ;init porta banksel lata ;data latch clrf lata ; banksel ansela ; clrf ansela ;digital i/o banksel trisa ; movlw b'00111000' ;set ra<5:3> as inputs movwf trisa ;and set ra<2:0> as ;outputs table 11-2: porta output priority pin name function priority (1) ra0 icspdat dac1out1 ra0 ra1 ra1 ra2 dac1out2 clc1 (2) c1out pwm3 ra2 ra3 none ra4 clkout sosco ra4 ra5 sosci ra5 note 1: priority listed from highest to lowest. 2: default pin (see apfcon register). 3: alternate pin (see apfcon register).
pic16(l)f1508/9 ds40001609b-page 112 ? 2011-2013 microchip technology inc. 11.4 register definitions: porta register 11-2: porta: porta register u-0 u-0 r/w-x/x r/w-x/x r-x/x r/w-x/x r/w-x/x r/w-x/x ? ? ra5 ra4 ra3 ra2 ra1 ra0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 ra<5:0> : porta i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 11-3: trisa: porta tri-state register u-0 u-0 r/w-1/1 r/w-1/1 u-1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 trisa<5:4>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output bit 3 unimplemented: read as ? 1 ? bit 2-0 trisa<2:0>: porta tri-state control bit 1 = porta pin configured as an input (tri-stated) 0 = porta pin configured as an output note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 113 pic16(l)f1508/9 register 11-4: lata: porta data latch register u-0 u-0 r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u ? ?lata5lata4 ? lata2 lata1 lata0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 lata<5:4> : ra<5:4> output latch value bits (1) bit 3 unimplemented: read as ? 0 ? bit 2-0 lata<2:0> : ra<2:0> output latch value bits (1) note 1: writes to porta are actually written to corresponding lata register. reads from porta register is return of actual i/o pin values. register 11-5: ansela: porta analog select register u-0 u-0 u-0 r/w-1/1 u-0 r/w-1/1 r/w-1/1 r/w-1/1 ? ? ? ansa4 ? ansa2 ansa1 ansa0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4 ansa4 : analog select between analog or digital function on pins ra4, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3 unimplemented: read as ? 0 ? bit 2-0 ansa<2:0> : analog select between analog or digital function on pins ra<2:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
pic16(l)f1508/9 ds40001609b-page 114 ? 2011-2013 microchip technology inc. table 11-3: summary of regist ers associated with porta table 11-4: summary of conf iguration word with porta register 11-6: wpua: weak pull-up porta register u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 wpua<5:0> : weak pull-up register bits (3) 1 = pull-up enabled 0 = pull-up disabled note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is configured as an output. 3: for the wpua3 bit, when mclre = 1 , weak pull-up is internally enabled, but not reported here. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 113 apfcon ? ? ? sssel t1gsel ? clc1sel nco1sel 110 lata ? ?lata5lata4 ?lata2lata1lata0 113 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 161 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 112 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 wpua ? ? wpua5 wpua4 wpua3 wpua2 wpua1 wpua0 114 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by porta. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by porta.
? 2011-2013 microchip technology inc. ds40001609b-page 115 pic16(l)f1508/9 11.5 portb registers 11.5.1 data register portb is a 4-bit wide, bidirectional port. the corresponding data direction register is trisb ( register 11-8 ). setting a trisb bit (= 1 ) will make the corresponding portb pin an input (i.e., disable the output driver). clearing a trisb bit (= 0 ) will make the corresponding portb pin an output (i.e., enables output driver and puts the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portb register ( register 11-7 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latb). 11.5.2 direction control the trisb register ( register 11-8 ) controls the portb pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisb register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.5.3 analog control the anselb register ( register 11-10 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselb bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselb bits has no effect on digital output functions. a pin with tris clear and ansel set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when executing read-modify-write instructions on the affected port. 11.5.4 portb functions and output priorities each portb pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-5 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input functions, such as adc and comparator inputs, are not shown in the priority lists. these inputs are active when the i/o pin is set for analog mode using the anselx registers. digital output functions may control the pin when it is in analog mode with the priority shown below in table 11-5 . note: the anselb bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 11-5: portb output priority pin name function priority (1) rb4 sda rb4 rb5 rb5 rb6 scl sck rb6 rb7 clc3 tx rb7 note 1: priority listed from highest to lowest. 2: default pin (see apfcon register). 3: alternate pin (see apfcon register).
pic16(l)f1508/9 ds40001609b-page 116 ? 2011-2013 microchip technology inc. 11.6 register definitions: portb register 11-7: portb: portb register r/w-x/x r/w-x/x r/w-x/x r/w-x/x u-0 u-0 u-0 u-0 rb7 rb6 rb5 rb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 rb<7:4> : portb i/o value bits (1) 1 = port pin is > v ih 0 = port pin is < v il bit 3-0 unimplemented: read as ? 0 ? note 1: writes to portb are actually written to corresponding latb register. reads from portb register is return of actual i/o pin values. register 11-8: trisb: portb tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 trisb7 trisb6 trisb5 trisb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 rb<7:4> : portb tri-state control bits 1 = portb pin configured as an input (tri-stated) 0 = portb pin configured as an output bit 3-0 unimplemented: read as ? 0 ?
? 2011-2013 microchip technology inc. ds40001609b-page 117 pic16(l)f1508/9 register 11-9: latb: portb data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 latb7 latb6 latb5 latb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 latb<7:4> : rb<7:4> output latch value bits (1) bit 3-0 unimplemented: read as ? 0 ? note 1: writes to portb are actually written to corresponding latb register. reads from portb register is return of actual i/o pin values. register 11-10: anselb: portb analog select register u-0 u-0 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 ? ? ansb5 ansb4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-4 ansb<5:4> : analog select between analog or digital function on pins rb<5:4>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 3-0 unimplemented: read as ? 0 ? note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin.
pic16(l)f1508/9 ds40001609b-page 118 ? 2011-2013 microchip technology inc. table 11-6: summary of regist ers associated with portb table 11-7: summary of conf iguration word with portb register 11-11: wpub: weak pull-up portb register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 u-0 u-0 u-0 u-0 wpub7 wpub6 wpub5 wpub4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 wpub<7:4> : weak pull-up register bits 1 = pull-up enabled 0 = pull-up disabled bit 3-0 unimplemented: read as ? 0 ? note 1: global wpuen bit of the option_reg register must be cleared for individual pull-ups to be enabled. 2: the weak pull-up device is automatically disabled if the pin is configured as an output. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselb ? ? ansb5 ansb4 ? ? ? ? 117 apfcon ? ? ? sssel t1gsel ? clc1sel nco1sel 110 latb latb7 latb6 latb5 latb4 ? ? ? ? 117 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 161 portb rb7 rb6 rb5 rb4 ? ? ? ? 116 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 116 wpub wpub7 wpub6 wpub5 wpub4 ? ? ? ? 118 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by portb. note 1: unimplemented, read as ? 1 ?. name bits bit -/7 bit -/6 bit 13/5 bit 12/4 bit 11/3 bit 10/2 bit 9/1 bit 8/0 register on page config1 13:8 ? ? fcmen ieso clkouten boren<1:0> ? 42 7:0 cp mclre pwrte wdte<1:0> fosc<2:0> legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by portb.
? 2011-2013 microchip technology inc. ds40001609b-page 119 pic16(l)f1508/9 11.7 portc registers 11.7.1 data register portc is a 8-bit wide, bidirectional port. the corresponding data direction register is trisc ( register 11-13 ). setting a trisc bit (= 1 ) will make the corresponding portc pin an input (i.e., disable the output driver). clearing a trisc bit (= 0 ) will make the corresponding portc pin an output (i.e., enable the output driver and put the contents of the output latch on the selected pin). example 11-1 shows how to initialize an i/o port. reading the portc register ( register 11-12 ) reads the status of the pins, whereas writing to it will write to the port latch. all write operations are read-modify-write operations. therefore, a write to a port implies that the port pins are read, this value is modified and then written to the port data latch (latc). 11.7.2 direction control the trisc register ( register 11-13 ) controls the portc pin output drivers, even when they are being used as analog inputs. the user should ensure the bits in the trisc register are maintained set when using them as analog inputs. i/o pins configured as analog input always read ? 0 ?. 11.7.3 analog control the anselc register ( register 11-15 ) is used to configure the input mode of an i/o pin to analog. setting the appropriate anselc bit high will cause all digital reads on the pin to be read as ? 0 ? and allow analog functions on the pin to operate correctly. the state of the anselc bits has no effect on digital out- put functions. a pin with tris clear and anselc set will still operate as a digital output, but the input mode will be analog. this can cause unexpected behavior when exe- cuting read-modify-write instructions on the affected port. 11.7.4 portc functions and output priorities each portc pin is multiplexed with other functions. the pins, their combined functions and their output priorities are shown in table 11-8 . when multiple outputs are enabled, the actual pin control goes to the peripheral with the highest priority. analog input and some digital input functions are not included in the output priority list. these input functions can remain active when the pin is configured as an output. certain digital input functions override other port functions and are included in the output priority list. note: the anselc bits default to the analog mode after reset. to use any pins as digital general purpose or peripheral inputs, the corresponding ansel bits must be initialized to ? 0 ? by user software. table 11-8: portc output priority pin name function priority (1) rc0 clc2 rc0 rc1 nco1 (2) pwm4 rc1 rc2 rc2 rc3 pwm2 rc3 rc4 cwg1b clc4 c2out rc4 rc5 cwg1a clc1 (3) pwm1 rc5 rc6 nco1 (3) rc6 rc7 sdo rc7 note 1: priority listed from highest to lowest. 2: default pin (see apfcon register). 3: alternate pin (see apfcon register).
pic16(l)f1508/9 ds40001609b-page 120 ? 2011-2013 microchip technology inc. 11.8 register definitions: portc register 11-12: portc: portc register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 rc<7:0> : portc general purpose i/o pin bits 1 = port pin is > v ih 0 = port pin is < v il register 11-13: trisc: portc tri-state register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 trisc<7:0>: portc tri-state control bits 1 = portc pin configured as an input (tri-stated) 0 = portc pin configured as an output register 11-14: latc: portc data latch register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 latc<7:0> : portc output latch value bits (1) note 1: writes to portc are actually written to corresponding latc register. reads from portc register is return of actual i/o pin values.
? 2011-2013 microchip technology inc. ds40001609b-page 121 pic16(l)f1508/9 table 11-9: summary of regist ers associated with portc register 11-15: anselc: portc analog select register r/w-1/1 r/w-1/1 u-0 u-0 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 ansc<7:6> : analog select between analog or digital function on pins rc<7:6>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. bit 5-4 unimplemented: read as ? 0 ? bit 3-0 ansc<3:0> : analog select between analog or digital function on pins rc<3:0>, respectively 1 = analog input. pin is assigned as analog input (1) . digital input buffer disabled. 0 = digital i/o. pin is assigned to port or digital special function. note 1: when setting a pin to an analog input, the corresponding tris bit must be set to input mode in order to allow external control of the voltage on the pin. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page anselc ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 121 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 120 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 120 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: x = unknown, u = unchanged, - = unimplemented locations read as ? 0 ?. shaded cells are not used by portc.
pic16(l)f1508/9 ds40001609b-page 122 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 123 pic16(l)f1508/9 12.0 interrupt-on-change the porta and portb pins can be configured to operate as interrupt-on-change (ioc) pins. an interrupt can be generated by detecting a signal that has either a rising edge or a falling edge. any individual port pin, or combination of port pins, can be configured to generate an interrupt. the interrupt-on-change module has the following features: ? interrupt-on-change enable (master switch) ? individual pin configuration ? rising and falling edge detection ? individual pin interrupt flags figure 12-1 is a block diagram of the ioc module. 12.1 enabling the module to allow individual port pins to generate an interrupt, the iocie bit of the intcon register must be set. if the iocie bit is disabled, the edge detection on the pin will still occur, but an interrupt will not be generated. 12.2 individual pin configuration for each port pin, a rising edge detector and a falling edge detector are present. to enable a pin to detect a rising edge, the associated bit of the iocxp register is set. to enable a pin to detect a falling edge, the associated bit of the iocxn register is set. a pin can be configured to detect rising and falling edges simultaneously by setting both associated bits of the iocxp and iocxn registers, respectively. 12.3 interrupt flags the iocafx and iocbfx bits located in the iocaf and iocbf registers, respectively, are status flags that correspond to the interrupt-on-change pins of the associated port. if an expected edge is detected on an appropriately enabled pin, then the status flag for that pin will be set, and an interrupt will be generated if the iocie bit is set. the iocif bit of the intcon register reflects the status of all iocafx and iocbfx bits. 12.4 clearing interrupt flags the individual status flags, (iocafx and iocbfx bits), can be cleared by resetting them to zero. if another edge is detected during this clearing operation, the associated status flag will be set at the end of the sequence, regardless of the value actually being written. in order to ensure that no detected edge is lost while clearing flags, only and operations masking out known changed bits should be performed. the following sequence is an example of what should be performed. example 12-1: clearing interrupt flags (porta example) 12.5 operation in sleep the interrupt-on-change interrupt sequence will wake the device from sleep mode, if the iocie bit is set. if an edge is detected while in sleep mode, the iocxf register will be updated prior to the first instruction executed out of sleep. movlw 0xff xorwf iocaf, w andwf iocaf, f
pic16(l)f1508/9 ds40001609b-page 124 ? 2011-2013 microchip technology inc. figure 12-1: interrupt-on-change bl ock diagram (porta example) iocanx iocapx q2 q4q1 data bus = 0 or 1 write iocafx iocie to data bus iocafx edge detect ioc interrupt to cpu core from all other iocnfx individual pin detectors dq r s dq r dq r rax q1 q2 q3 q4 q4q1 q1 q2 q3 q4 q1 q2 q3 q4 q4q1 q4q1 q4q1 f osc rev. 10-000037a_a0
? 2011-2013 microchip technology inc. ds40001609b-page 125 pic16(l)f1508/9 12.6 register definitions: interrupt-on-change control register 12-1: iocap: interrupt-on-c hange porta positive edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocap<5:0>: interrupt-on-change porta positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-2: iocan: interrupt-on-change porta negative edge register u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocan<5:0>: interrupt-on-change porta negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocafx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. register 12-3: iocaf: interrupt- on-change porta flag register u-0 u-0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0 /0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-6 unimplemented: read as ? 0 ? bit 5-0 iocaf<5:0>: interrupt-on-change porta flag bits 1 = an enabled change was detected on the associated pin. set when iocapx = 1 and a rising edge was detected on rax, or when iocanx = 1 and a falling edge was detected on rax. 0 = no change was detected, or the user cleared the detected change.
pic16(l)f1508/9 ds40001609b-page 126 ? 2011-2013 microchip technology inc. register 12-4: iocbp: interrupt-on-c hange portb positive edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 iocbp7 iocbp6 iocbp5 iocbp4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 iocbp<7:4>: interrupt-on-change portb positive edge enable bits 1 = interrupt-on-change enabled on the pin for a positive going edge. iocbfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. bit 3-0 unimplemented: read as ? 0 ? register 12-5: iocbn: interrupt-on-change portb negative edge register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 iocbn7 iocbn6 iocbn5 iocbn4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 iocbn<7:4>: interrupt-on-change portb negative edge enable bits 1 = interrupt-on-change enabled on the pin for a negative going edge. iocbfx bit and iocif flag will be set upon detecting an edge. 0 = interrupt-on-change disabled for the associated pin. bit 3-0 unimplemented: read as ? 0 ? register 12-6: iocbf: interrupt- on-change portb flag register r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 r/w/hs-0/0 u-0 u-0 u-0 u-0 iocbf7 iocbf6 iocbf5 iocbf4 ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs - bit is set in hardware bit 7-4 iocbf<7:4>: interrupt-on-change portb flag bits 1 = an enabled change was detected on the associated pin. set when iocbpx = 1 and a rising edge was detected on rbx, or when iocbnx = 1 and a falling edge was detected on rbx. 0 = no change was detected, or the user cleared the detected change. bit 3-0 unimplemented: read as ? 0 ?
? 2011-2013 microchip technology inc. ds40001609b-page 127 pic16(l)f1508/9 table 12-1: summary of registers as sociated with interrupt-on-change name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 113 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 iocaf ? ? iocaf5 iocaf4 iocaf3 iocaf2 iocaf1 iocaf0 125 iocan ? ? iocan5 iocan4 iocan3 iocan2 iocan1 iocan0 125 iocap ? ? iocap5 iocap4 iocap3 iocap2 iocap1 iocap0 125 iocbf iocbf7 iocbf6 iocbf5 iocbf4 ? ? ? ? 126 iocbn iocbn7 iocbn6 iocbn5 iocbn4 ? ? ? ? 126 iocbp iocbp7 iocbp6 iocbp5 iocbp4 ? ? ? ? 126 trisa ? ? trisa5 trisa4 ?(1) trisa2 trisa1 trisa0 112 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 116 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by interrupt-on-change. note 1: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 128 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 129 pic16(l)f1508/9 13.0 fixed voltage reference (fvr) the fixed voltage reference (fvr) is a stable voltage reference, independent of v dd , with a nominal output level ( v fvr ) of 1.024v. the output of the fvr can be configured to supply a reference voltage to the following: ? adc input channel ? comparator positive input ? comparator negative input the fvr can be enabled by setting the fvren bit of the fvrcon register. 13.1 independent gain amplifier the output of the fvr supplied to the peripherals, (listed above), is routed through a programmable gain amplifier. each amplifier can be programmed for a gain of 1x, 2x or 4x, to produce the three possible voltage levels. the adfvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the adc module. refer- ence section 15.0 ?analog-to-digital converter (adc) module? for additional information. the cdafvr<1:0> bits of the fvrcon register are used to enable and configure the gain amplifier settings for the reference supplied to the comparator modules. reference section 17.0 ?comparator module? for additional information. 13.2 fvr stabilization period when the fixed voltage reference module is enabled, it requires time for the reference and amplifier circuits to stabilize. once the circuits stabilize and are ready for use, the fvrrdy bit of the fvrcon register will be set. see the fvr stabilization period characterization graph, figure 30-65 . figure 13-1: voltage reference block diagram adfvr<1:0> cdafvr<1:0> x 1 x 2 x 4 x 1 x 2 x 4 2 2 fvr_buffer1 (to adc module) fvr_buffer2 (to comparators) + _ fvren fvrrdy any peripheral requiring the fixed reference (see table 13-1 ) v adfvr v cdafvr v fvr table 13-1: peripherals requiring the fixed voltage reference (fvr) peripheral conditions description hfintosc fosc<2:0> = 010 and ircf<3:0> = 000x intosc is active and device is not in sleep. bor boren<1:0> = 11 bor always enabled. boren<1:0> = 10 and borfs = 1 bor disabled in sleep mode, bor fast start enabled. boren<1:0> = 01 and borfs = 1 bor under software control, bor fast start enabled. ldo all pic16f1508/9 devices, when vregpm = 1 and not in sleep the device runs off of the low-power regulator when in sleep mode.
pic16(l)f1508/9 ds40001609b-page 130 ? 2011-2013 microchip technology inc. 13.3 register definitions: fvr control table 13-2: summary of registers associated with the fixed voltage reference register 13-1: fvrcon: fixed voltage reference control register r/w-0/0 r-q/q r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 fvren fvrrdy (1) tsen (3) tsrng (3) cdafvr<1:0> adfvr<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 fvren: fixed voltage reference enable bit 1 = fixed voltage reference is enabled 0 = fixed voltage reference is disabled bit 6 fvrrdy: fixed voltage reference ready flag bit (1) 1 = fixed voltage reference output is ready for use 0 = fixed voltage reference output is not ready or not enabled bit 5 tsen: temperature indicator enable bit (3) 1 = temperature indicator is enabled 0 = temperature indicator is disabled bit 4 tsrng: temperature indicator range selection bit (3) 1 =v out = v dd - 4v t (high range) 0 =v out = v dd - 2v t (low range) bit 3-2 cdafvr<1:0>: comparator fvr buffer gain selection bits 11 = comparator fvr buffer gain is 4x, with output v cdafvr = 4x v fvr (2) 10 = comparator fvr buffer gain is 2x, with output v cdafvr = 2x v fvr (2) 01 = comparator fvr buffer gain is 1x, with output v cdafvr = 1x v fvr 00 = comparator fvr buffer is off bit 1-0 adfvr<1:0>: adc fvr buffer gain selection bit 11 = adc fvr buffer gain is 4x, with output v adfvr = 4x v fvr (2) 10 = adc fvr buffer gain is 2x, with output v adfvr = 2x v fvr (2) 01 = adc fvr buffer gain is 1x, with output v adfvr = 1x v fvr 00 = adc fvr buffer is off note 1: fvrrdy is always ? 1 ? for the pic16f1508/9 devices. 2: fixed voltage reference output cannot exceed v dd . 3: see section 14.0 ?temperature indicator module? for additional information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr>1:0> adfvr<1:0> 130 legend: shaded cells are unused by the fixed voltage reference module.
? 2011-2013 microchip technology inc. ds40001609b-page 131 pic16(l)f1508/9 14.0 temperature indicator module this family of devices is equipped with a temperature circuit designed to measure the operating temperature of the silicon die. the circuit?s range of operating temperature falls between -40c and +85c. the output is a voltage that is proportional to the device temperature. the output of the temperature indicator is internally connected to the device adc. the circuit may be used as a temperature threshold detector or a more accurate temperature indicator, depending on the level of calibration performed. a one- point calibration allows the circuit to indicate a temperature closely surrounding that point. a two-point calibration allows the circuit to sense the entire range of temperature more accurately. reference application note an1333, ? use and calibration of the internal temperature indicator ? (ds01333) for more details regarding the calibration process. 14.1 circuit operation figure 14-1 shows a simplified block diagram of the temperature circuit. the proportional voltage output is achieved by measuring the forward voltage drop across multiple silicon junctions. equation 14-1 describes the output characteristics of the temperature indicator. equation 14-1: v out ranges the temperature sense circuit is integrated with the fixed voltage reference (fvr) module. see section 13.0 ?fixed voltage reference (fvr)? for more information. the circuit is enabled by setting the tsen bit of the fvrcon register. when disabled, the circuit draws no current. the circuit operates in either high or low range. the high range, selected by setting the tsrng bit of the fvrcon register, provides a wider output voltage. this provides more resolution over the temperature range, but may be less consistent from part to part. this range requires a higher bias voltage to operate and thus, a higher v dd is needed. the low range is selected by clearing the tsrng bit of the fvrcon register. the low range generates a lower voltage drop and thus, a lower bias voltage is needed to operate the circuit. the low range is provided for low voltage operation. figure 14-1: temperature circuit diagram 14.2 minimum operating v dd when the temperature circuit is operated in low range, the device may be operated at any operating voltage that is within specifications. when the temperature circuit is operated in high range, the device operating voltage, v dd , must be high enough to ensure that the temperature circuit is cor- rectly biased. table 14-1 shows the recommended minimum v dd vs. range setting. table 14-1: recommended v dd vs. range 14.3 temperature output the output of the circuit is measured using the internal analog-to-digital converter. a channel is reserved for the temperature circuit output. refer to section 15.0 ?analog-to-digital converter (adc) module? for detailed information. 14.4 adc acquisition time to ensure accurate temperature measurements, the user must wait at least 200 ? s after the adc input multiplexer is connected to the temperature indicator output before the conversion is performed. in addition, the user must wait 200 ? s between sequential conversions of the temperature indicator output. high range: v out = v dd - 4v t low range: v out = v dd - 2v t min. v dd , tsrng = 1 min. v dd , tsrng = 0 3.6v 1.8v tsen tsrng v dd v out to a d c temp. indicator
pic16(l)f1508/9 ds40001609b-page 132 ? 2011-2013 microchip technology inc. table 14-2: summary of registers associated with the temperature indicator name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 118 legend: shaded cells are unused by the temperature indicator module.
? 2011-2013 microchip technology inc. ds40001609b-page 133 pic16(l)f1508/9 15.0 analog-to-digital converter (adc) module the analog-to-digital converter (adc) allows conversion of an analog input signal to a 10-bit binary representation of that signal. this device uses analog inputs, which are multiplexed into a single sample and hold circuit. the output of the sample and hold is connected to the input of the converter. the converter generates a 10-bit binary result via successive approximation and stores the conversion result into the adc result registers (adresh:adresl register pair). figure 15-1 shows the block diagram of the adc. the adc voltage reference is software selectable to be either internally generated or externally supplied. the adc can generate an interrupt upon completion of a conversion. this interrupt can be used to wake-up the device from sleep. figure 15-1: adc block diagram vref+ vref- enable dacx_output fvr_buffer1 temp indicator chs<4:0> external channel inputs go/done complete start adc sample circuit write to bit go/done v ss v dd v ref + pin v dd adpref 10-bit result adresh adresl 16 adfm 10 internal channel inputs . . . an0 ana anz set bit adif v ss adon sampled input q1 q2 q4 fosc divider f osc f osc /n f rc adc clock select adc_clk adcs<2:0> f rc adc clock source trigger select trigger sources . . . trigsel<3:0> auto conversion trigger positive reference select rev. 10-000033a_a0
pic16(l)f1508/9 ds40001609b-page 134 ? 2011-2013 microchip technology inc. 15.1 adc configuration when configuring and using the adc the following functions must be considered: ? port configuration ? channel selection ? adc voltage reference selection ? adc conversion clock source ? interrupt control ? result formatting 15.1.1 port configuration the adc can be used to convert both analog and digital signals. when converting analog signals, the i/o pin should be configured for analog by setting the associated tris and ansel bits. refer to section 11.0 ?i/o ports? for more information. 15.1.2 channel selection there are 15 channel selections available: ?an<11:0> pins ? temperature indicator ? dac1_output ? fvr_buffer1 the chs bits of the adcon0 register determine which channel is connected to the sample and hold circuit. when changing channels, a delay (t acq ) is required before starting the next conversion. refer to section 15.2.6 ?adc conversion procedure? for more information. 15.1.3 adc voltage reference the adc module uses a positive and a negative voltage reference. the positive reference is labeled ref+ and the negative reference is labeled ref-. the positive voltage reference (ref+) is selected by the adpref bits in the adcon1 register. the positive voltage reference source can be: ?v ref + pin ?v dd the negative voltage reference (ref-) source is: ?v ss 15.1.4 conversion clock the source of the conversion clock is software select- able via the adcs bits of the adcon1 register. there are seven possible clock options: ?f osc /2 ?f osc /4 ?f osc /8 ?f osc /16 ?f osc /32 ?f osc /64 ? frc (internal rc oscillator) the time to complete one bit conversion is defined as t ad . one full 10-bit conversion requires 11.5 t ad peri- ods as shown in figure 15-2 . for correct conversion, the appropriate t ad specifica- tion must be met. refer to the adc conversion require- ments in section 29.0 ?electrical specifications? for more information. table 15-1 gives examples of appro- priate adc clock selections. note: analog voltages on any pin that is defined as a digital input may cause the input buffer to conduct excess current. note: unless using the frc, any changes in the system clock frequency will change the adc clock frequency, which may adversely affect the adc result.
? 2011-2013 microchip technology inc. ds40001609b-page 135 pic16(l)f1508/9 table 15-1: adc clock period (t ad ) v s . device operating frequencies figure 15-2: analog-to-dig ital conversion t ad cycles adc clock period (t ad ) device frequency (f osc ) adc clock source adcs<2:0 > 20 mhz 16 mhz 8 mhz 4 mhz 1 mhz fosc/2 000 100 ns 125 ns 250 ns 500 ns 2.0 ? s fosc/4 100 200 ns 250 ns 500 ns 1.0 ? s4.0 ? s fosc/8 001 400 ns 500 ns 1.0 ? s2.0 ? s 8.0 ? s fosc/16 101 800 ns 1.0 ? s2.0 ? s4.0 ? s 16.0 ? s fosc/32 010 1.6 ? s2.0 ? s4.0 ? s 8.0 ? s 32.0 ? s fosc/64 110 3.2 ? s4.0 ? s 8.0 ? s 16.0 ? s 64.0 ? s frc x11 1.0-6.0 ? s 1.0-6.0 ? s 1.0-6.0 ? s 1.0-6.0 ? s 1.0-6.0 ? s legend: shaded cells are outside of recommended range. note: the t ad period when using the frc clock source can fall within a specified range, (see t ad parameter). the t ad period when using the f osc -based clock source can be configured for a more precise t ad period. however, the frc clock source must be used when conversions are to be performed with the device in sleep mode. t ad 1 t ad 2 t ad 3 t ad 4 t ad 5 t ad 6 t ad 7 t ad 8 t ad 9 t ad 10 t ad 11 set go bit conversion starts holding capacitor disconnected from analog input (thcd). on the following cycle: adresh:adresl is loaded, go bit is cleared, adif bit is set, holding capacitor is reconnected to analog input. b9 b8 b7 b6 b5 b4 b3 b2 b1 b0 enable adc (adon bit) and select channel (acs bits) t hcd t acq rev. 10-000035a_a0
pic16(l)f1508/9 ds40001609b-page 136 ? 2011-2013 microchip technology inc. 15.1.5 interrupts the adc module allows for the ability to generate an interrupt upon completion of an analog-to-digital conversion. the adc interrupt flag is the adif bit in the pir1 register. the adc interrupt enable is the adie bit in the pie1 register. the adif bit must be cleared in software. this interrupt can be generated while the device is operating or while in sleep. if the device is in sleep, the interrupt will wake-up the device. upon waking from sleep, the next instruction following the sleep instruc- tion is always executed. if the user is attempting to wake-up from sleep and resume in-line code execu- tion, the gie and peie bits of the intcon register must be disabled. if the gie and peie bits of the intcon register are enabled, execution will switch to the interrupt service routine. 15.1.6 result formatting the 10-bit adc conversion result can be supplied in two formats, left justified or right justified. the adfm bit of the adcon1 register controls the output format. figure 15-3 shows the two output formats. figure 15-3: 10-bit adc conv ersion result format note 1: the adif bit is set at the completion of every conversion, regardless of whether or not the adc interrupt is enabled. 2: the adc operates during sleep only when the frc oscillator is selected. adresh adresl (adfm = 0 )msb lsb bit 7 bit 0 bit 7 bit 0 10-bit adc result unimplemented: read as ? 0 ? (adfm = 1 ) msb lsb bit 7 bit 0 bit 7 bit 0 unimplemented: read as ? 0 ? 10-bit adc result
? 2011-2013 microchip technology inc. ds40001609b-page 137 pic16(l)f1508/9 15.2 adc operation 15.2.1 starting a conversion to enable the adc module, the adon bit of the adcon0 register must be set to a ? 1 ?. setting the go/ done bit of the adcon0 register to a ? 1 ? will start the analog-to-digital conversion. 15.2.2 completion of a conversion when the conversion is complete, the adc module will: ? clear the go/done bit ? set the adif interrupt flag bit ? update the adresh and adresl registers with new conversion result 15.2.3 terminating a conversion if a conversion must be terminated before completion, the go/done bit can be cleared in software. the adresh and adresl registers will be updated with the partially complete analog-to-digital conversion sample. incomplete bits will match the last bit converted. 15.2.4 adc operation during sleep the adc module can operate during sleep. this requires the adc clock source to be set to the frc option. performing the adc conversion during sleep can reduce system noise. if the adc interrupt is enabled, the device will wake-up from sleep when the conversion completes. if the adc interrupt is disabled, the adc module is turned off after the conversion com- pletes, although the adon bit remains set. when the adc clock source is something other than frc, a sleep instruction causes the present conver- sion to be aborted and the adc module is turned off, although the adon bit remains set. 15.2.5 auto-conversion trigger the auto-conversion trigger allows periodic adc mea- surements without software intervention. when a rising edge of the selected source occurs, the go/done bit is set by hardware. the auto-conversion trigger source is selected with the trigsel<3:0> bits of the adcon2 register. using the auto-conversion trigger does not assure proper adc timing. it is the user?s responsibility to ensure that the adc timing requirements are met. see table 15-2 for auto-conversion sources. note: the go/done bit should not be set in the same instruction that turns on the adc. refer to section 15.2.6 ?adc conver- sion procedure? . note: a device reset forces all registers to their reset state. thus, the adc module is turned off and any pending conversion is terminated. table 15-2: auto-conversion sources source peripheral signal name timer0 t0_overflow timer1 t1_overflow timer2 t2_match comparator c1 c1out_sync comparator c2 c2out_sync clc1 lc1_out clc2 lc2_out clc3 lc3_out clc4 lc4_out
pic16(l)f1508/9 ds40001609b-page 138 ? 2011-2013 microchip technology inc. 15.2.6 adc conversion procedure this is an example procedure for using the adc to perform an analog-to-digital conversion: 1. configure port: ? disable pin output driver (refer to the tris register) ? configure pin as analog (refer to the ansel register) 2. configure the adc module: ? select adc conversion clock ? configure voltage reference ? select adc input channel ? turn on adc module 3. configure adc interrupt (optional): ? clear adc interrupt flag ? enable adc interrupt ? enable peripheral interrupt ? enable global interrupt (1) 4. wait the required acquisition time (2) . 5. start conversion by setting the go/done bit. 6. wait for adc conversion to complete by one of the following: ? polling the go/done bit ? waiting for the adc interrupt (interrupts enabled) 7. read adc result. 8. clear the adc interrupt flag (required if interrupt is enabled). example 15-1: adc conversion note 1: the global interrupt can be disabled if the user is attempting to wake-up from sleep and resume in-line code execution. 2: refer to section 15.4 ?adc acquisi- tion requirements? . ;this code block configures the adc ;for polling, vdd and vss references, frc ;oscillator and an0 input. ; ;conversion start & polling for completion ; are included. ; banksel adcon1 ; movlw b?11110000? ;right justify, frc ;oscillator movwf adcon1 ;vdd and vss vref+ banksel trisa ; bsf trisa,0 ;set ra0 to input banksel ansel ; bsf ansel,0 ;set ra0 to analog banksel adcon0 ; movlw b?00000001? ;select channel an0 movwf adcon0 ;turn adc on call sampletime ;acquisiton delay bsf adcon0,adgo ;start conversion btfsc adcon0,adgo ;is conversion done? goto $-1 ;no, test again banksel adresh ; movf adresh,w ;read upper 2 bits movwf resulthi ;store in gpr space banksel adresl ; movf adresl,w ;read lower 8 bits movwf resultlo ;store in gpr space
? 2011-2013 microchip technology inc. ds40001609b-page 139 pic16(l)f1508/9 15.3 register definitions: adc control register 15-1: adcon0: ad c control register 0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? chs<4:0> go/done adon bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-2 chs<4:0>: analog channel select bits 00000 =an0 00001 =an1 00010 =an2 00011 =an3 00100 =an4 00101 =an5 00110 =an6 00111 =an7 01000 =an8 01001 =an9 01010 =an10 01011 =an11 01100 = reserved. no channel connected. ? ? ? 11100 = reserved. no channel connected. 11101 = temperature indicator (1) 11110 = dac (digital-to-analog converter) (2) 11111 = fvr (fixed voltage reference) buffer 1 output (3) bit 1 go/done : adc conversion status bit 1 = adc conversion cycle in progress. setting this bit starts an adc conversion cycle. this bit is automatically cleared by hardware when the adc conversion has completed. 0 = adc conversion completed/not in progress bit 0 adon: adc enable bit 1 = adc is enabled 0 = adc is disabled and consumes no operating current note 1: see section 14.0 ?temperature indicator module? for more information. 2: see section 16.0 ?5-bit digital-to-analog converter (dac) module? for more information. 3: see section 13.0 ?fixed voltage reference (fvr)? for more information.
pic16(l)f1508/9 ds40001609b-page 140 ? 2011-2013 microchip technology inc. register 15-2: adcon1: ad c control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 adfm adcs<2:0> ? ? adpref<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 adfm: adc result format select bit 1 = right justified. six most significant bits of adresh are set to ? 0 ? when the conversion result is loaded. 0 = left justified. six least significant bits of adresl are set to ? 0 ? when the conversion result is loaded. bit 6-4 adcs<2:0>: adc conversion clock select bits 000 =f osc /2 001 =f osc /8 010 =f osc /32 011 = frc (clock supplied from an internal rc oscillator) 100 =f osc /4 101 =f osc /16 110 =f osc /64 111 = frc (clock supplied from an internal rc oscillator) bit 3-2 unimplemented : read as ? 0 ? bit 1-0 adpref<1:0>: adc positive voltage reference configuration bits 00 =v ref + is connected to v dd 01 = reserved 10 =v ref + is connected to external v ref + pin (1) 11 = reserved note 1: when selecting the v ref + pin as the source of the positive reference, be aware that a minimum voltage specification exists. see section 29.0 ?electrical specifications? for details.
? 2011-2013 microchip technology inc. ds40001609b-page 141 pic16(l)f1508/9 register 15-3: adcon2: ad c control register 2 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 u-0 trigsel<3:0> (1) ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 trigsel<3:0>: auto-conversion trigger selection bits (1) 0000 = no auto-conversion trigger selected 0001 =reserved 0010 =reserved 0011 = timer0 ? t0_overflow (2) 0100 = timer1 ? t1_overflow (2) 0101 = timer2 ? t2_match 0110 = comparator c1 ? c1out_sync 0111 = comparator c2 ? c2out_sync 1000 = clc1 ? lc1_out 1001 = clc2 ? lc2_out 1010 = clc3 ? lc3_out 1011 = clc4 ? lc4_out 1100 =reserved 1101 =reserved 1110 =reserved 1111 = reserved bit 3-0 unimplemented: read as ? 0 ? note 1: this is a rising edge sensitive input for all sources. 2: signal also sets its corresponding interrupt flag.
pic16(l)f1508/9 ds40001609b-page 142 ? 2011-2013 microchip technology inc. register 15-4: adresh: adc result register high (adresh) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<9:2> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<9:2> : adc result register bits upper eight bits of 10-bit conversion result register 15-5: adresl: adc result register low (adresl) adfm = 0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<1:0> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 adres<1:0> : adc result register bits lower two bits of 10-bit conversion result bit 5-0 reserved : do not use.
? 2011-2013 microchip technology inc. ds40001609b-page 143 pic16(l)f1508/9 register 15-6: adresh: adc result register high (adresh) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? ? ? ? ? adres<9:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 reserved : do not use. bit 1-0 adres<9:8> : adc result register bits upper two bits of 10-bit conversion result register 15-7: adresl: adc result register low (adresl) adfm = 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u adres<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 adres<7:0> : adc result register bits lower eight bits of 10-bit conversion result
pic16(l)f1508/9 ds40001609b-page 144 ? 2011-2013 microchip technology inc. 15.4 adc acquisition requirements for the adc to meet its specified accuracy, the charge holding capacitor (c hold ) must be allowed to fully charge to the input channel voltage level. the analog input model is shown in figure 15-4 . the source impedance (r s ) and the internal sampling switch (r ss ) impedance directly affect the time required to charge the capacitor c hold . the sampling switch (r ss ) impedance varies over the device voltage (v dd ), refer to figure 15-4 . the maximum recommended impedance for analog sources is 10 k ? . as the source impedance is decreased, the acquisition time may be decreased. after the analog input channel is selected (or changed), an adc acquisition must be done before the conversion can be started. to calculate the minimum acquisition time, equation 15-1 may be used. this equation assumes that 1/2 lsb error is used (1,024 steps for the adc). the 1/2 lsb error is the maximum error allowed for the adc to meet its specified resolution. equation 15-1: acquisition time example t acq amplifier settling time hold capacitor charging time temperature coefficient ++ = t amp t c t coff ++ = 2s t c temperature - 25c ?? 0.05s/c ?? ?? ++ = t c c hold r ic r ss r s ++ ?? ln(1/2047) ? = 12.5pf 1k ? 7k ? 10k ? ++ ?? ? ln(0.0004885) = 1.12 = s v applied 1e tc ? rc --------- ? ?? ?? ?? v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? = v applied 1 1 2 n1 + ?? 1 ? -------------------------- ? ?? ?? v chold = v applied 1e t c ? rc --------- - ? ?? ?? ?? v chold = ;[1] v chold charged to within 1/2 lsb ;[2] v chold charge response to v applied ;combining [1] and [2] the value for t c can be approximated with the following equations: solving for t c : therefore: temperature 50c and external impedance of 10k ? 5.0v v dd = assumptions: note: where n = number of bits of the adc. t acq 2s 1.12 s 50c- 25c ?? 0.05 s/c ?? ?? ++ = 4.37s = note 1: the reference voltage (v ref +) has no effect on the equation, since it cancels itself out. 2: the charge holding capacitor (c hold ) is not discharged after each conversion. 3: the maximum recommended impedance for analog sources is 10 k ? . this is required to meet the pin leakage specification.
? 2011-2013 microchip technology inc. ds40001609b-page 145 pic16(l)f1508/9 figure 15-4: analog input model figure 15-5: adc transfer function c pin va rs analog 5 pf v dd v t ? 0.6v v t ? 0.6v i leakage (1) r ic ? 1k sampling switch ss rss c hold = 10 pf ref- 6v sampling switch 5v 4v 3v 2v 567891011 (k ? ) v dd legend: c pin v t i leakage r ic ss c hold = input capacitance = threshold voltage = leakage current at the pin due to = interconnect resistance = sampling switch = sample/hold capacitance various junctions r ss note 1: refer to section 29.0 ?electrical specifications? . r ss = resistance of sampling switch input pin 3ffh 3feh adc output code 3fdh 3fch 03h 02h 01h 00h full-scale 3fbh 0.5 lsb ref- zero-scale transition ref+ transition 1.5 lsb full-scale range analog input voltage
pic16(l)f1508/9 ds40001609b-page 146 ? 2011-2013 microchip technology inc. table 15-3: summary of registers associated with adc name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon0 ? chs<4:0> go/done adon 139 adcon1 adfm adcs<2:0> ? ? adpref<1:0> 140 adcon2 trigsel<3:0> ? ? ? ? 141 adresh adc result register high 142 , 143 adresl adc result register low 142 , 143 ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 113 anselb ? ? ansb5 ansb4 ? ? ? ? 117 anselc ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 121 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 trisa ? ? trisa5 trisa4 ?(1) trisa2 trisa1 trisa0 112 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 116 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 130 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends on condition. shaded cells are not used for adc module. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 147 pic16(l)f1508/9 16.0 5-bit digital-to-analog converter (dac) module the digital-to-analog converter supplies a variable voltage reference, ratiometric with the input source, with 32 selectable output levels. the positive input source (v source +) of the dac can be connected to: ?external v ref + pin ?v dd supply voltage the negative input source (v source -) of the dac can be connected to: ?vss the output of the dac (dacx_output) can be selected as a reference voltage to the following: ? comparator positive input ? adc input channel ?dacxout1 pin ?dacxout2 pin the digital-to-analog converter (dac) can be enabled by setting the dacen bit of the dacxcon0 register. figure 16-1: digital-to-analog co nverter block diagram v ref + v dd dacpss v source + v source - v ss r 32 steps r r r r r r 32-to-1 mux to peripherals dacxout1 (1) dacoe1 dacx_output dacen dacr<4:0> 5 dacxout2 (1) dacoe2 0 1 note 1: the unbuffered dacx_output is provided on the dacxout pin(s). rev. 10-000026a_a0
pic16(l)f1508/9 ds40001609b-page 148 ? 2011-2013 microchip technology inc. 16.1 output voltage selection the dac has 32 voltage level ranges. the 32 levels are set with the dacr<4:0> bits of the dacxcon1 register. the dac output voltage can be determined by using equation 16-1 . 16.2 ratiometric output level the dac output value is derived using a resistor ladder with each end of the ladder tied to a positive and negative voltage reference input source. if the voltage of either input source fluctuates, a similar fluctuation will result in the dac output value. the value of the individual resistors within the ladder can be found in table 29-16 . 16.3 dac voltage reference output the unbuffered dac voltage can be output to the dacxoutn pin(s) by setting the respective dacoen bit(s) of the dacxcon0 register. selecting the dac reference voltage for output on either dacxoutn pin automatically overrides the digital output buffer, the weak pull-up and digital input threshold detector functions of that pin. reading the dacxoutn pin when it has been configured for dac reference voltage output will always return a ? 0 ?. 16.4 operation during sleep when the device wakes up from sleep through an interrupt or a watchdog timer time-out, the contents of the dacxcon0 register are not affected. to minimize current consumption in sleep mode, the voltage reference should be disabled. 16.5 effects of a reset a device reset affects the following: ? dacx is disabled. ?dac x output voltage is removed from the dacxoutn pin(s). ? the dacr<4:0> range select bits are cleared. equation 16-1: dac output voltage note: the unbuffered dac output (dacxoutn) is not intended to drive an external load. if dacen = 1 dacx_output v source +v source - ? ?? dacr 4:0 ?? 2 5 ----------------------------- ? ?? ?? v source - + = note: see the dacxcon0 register for the available v source + and v source - selections.
? 2011-2013 microchip technology inc. ds40001609b-page 149 pic16(l)f1508/9 16.6 register definitions: dac control table 16-1: summary of registers asso ciated with the dac module register 16-1: dacxcon0: voltage reference control register 0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 u-0 u-0 dacen ?dacoe1dacoe2 ?dacpss ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 dacen: dac enable bit 1 = dacx is enabled 0 = dacx is disabled bit 6 unimplemented: read as ? 0 ? bit 5 dacoe1: dac voltage output enable bit 1 = dacx voltage level is output on the dacxout1 pin 0 = dacx voltage level is disconnected from the dacxout1 pin bit 4 dacoe2: dac voltage output enable bit 1 = dacx voltage level is output on the dacxout2 pin 0 = dacx voltage level is disconnected from the dacxout2 pin bit 3 unimplemented: read as ? 0 ? bit 2 dacpss: dac positive source select bit 1 =v ref + pin 0 =v dd bit 1-0 unimplemented: read as ? 0 ? register 16-2: dacxcon1: voltage reference control register 1 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? dacr<4:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 unimplemented: read as ? 0 ? bit 4-0 dacr<4:0>: dac voltage output select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page dac1con0 dacen ? dacoe1 dacoe2 ?dacpss ? ? 149 dac1con1 ? ? ? dacr<4:0> 149 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used with the dac module.
pic16(l)f1508/9 ds40001609b-page 150 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 151 pic16(l)f1508/9 17.0 comparator module comparators are used to interface analog circuits to a digital circuit by comparing two analog voltages and providing a digital indication of their relative magnitudes. comparators are very useful mixed signal building blocks because they provide analog functionality independent of program execution. the analog comparator module includes the following features: ? independent comparator control ? programmable input selection ? comparator output is available internally/externally ? programmable output polarity ? interrupt-on-change ? wake-up from sleep ? programmable speed/power optimization ?pwm shutdown ? programmable and fixed voltage reference 17.1 comparator overview a single comparator is shown in figure 17-2 along with the relationship between the analog input levels and the digital output. when the analog voltage at v in + is less than the analog voltage at v in -, the output of the comparator is a digital low level. when the analog voltage at v in + is greater than the analog voltage at v in -, the output of the comparator is a digital high level. the comparators available for this device are listed in table 17-1 . figure 17-1: comparator module simplified block diagram table 17-1: available comparators device c1 c2 pic16(l)f1508 pic16(l)f1509 000 cxin0- cxin1- cxin2- cxin3- 00 01 10 11 cxin+ fvr_buffer2 dac_out + cxvn cxvp cxpch<1:0> cxnch<2:0> 2 3 cxon (1) cxon (1) cxon (1) cxsp cxhys interrupt rising edge dq q1 cxintp cxintn cxout mcxout cxout_async dq 0 1 cxsync set bit cxif tris bit cxout cxout_sync to peripherals cxoe - interrupt falling edge note 1: when cxon = 0 , all multiplexer inputs are disconnected and the comparator will produce a ? 0 ? at the output. fvr_buffer2 cxpol cx (from timer1 module) t1clk to peripherals 001 010 011 100 rev. 10-000027a_a0
pic16(l)f1508/9 ds40001609b-page 152 ? 2011-2013 microchip technology inc. figure 17-2: single comparator 17.2 comparator control each comparator has two control registers: cmxcon0 and cmxcon1. the cmxcon0 registers (see register 17-1 ) contain control and status bits for the following: ? enable ?output selection ? output polarity ? speed/power selection ? hysteresis enable ? output synchronization the cmxcon1 registers (see register 17-2 ) contain control bits for the following: ? interrupt enable ? interrupt edge polarity ? positive input channel selection ? negative input channel selection 17.2.1 comparator enable setting the cxon bit of the cmxcon0 register enables the comparator for operation. clearing the cxon bit disables the comparator resulting in minimum current consumption. 17.2.2 comparator positive input selection configuring the cxpch<1:0> bits of the cmxcon1 register directs an internal voltage reference or an analog pin to the non-inverting input of the comparator: ? cxin+ analog pin ? dac1_output ? fvr_buffer2 ?v ss see section 13.0 ?fixed voltage reference (fvr)? for more information on the fixed voltage reference module. see section 16.0 ?5-bit digital-to-analog converter (dac) module? for more information on the dac input signal. any time the comparator is disabled (cxon = 0 ), all comparator inputs are disabled. 17.2.3 comparator negative input selection the cxnch<2:0> bits of the cmxcon0 register direct one of the input sources to the comparator inverting input. 17.2.4 comparator output selection the output of the comparator can be monitored by reading either the cxout bit of the cmxcon0 register or the mcxout bit of the cmout register. in order to make the output available for an external connection, the following conditions must be true: ? cxoe bit of the cmxcon0 register must be set ? corresponding tris bit must be cleared ? cxon bit of the cmxcon0 register must be set the synchronous comparator output signal (cxout_sync) is available to the following peripheral(s): ? configurable logic cell (clc) ? analog-to-digital converter (adc) ?timer1 the asynchronous comparator output signal (cxout_async) is available to the following peripheral(s): ? complementary waveform generator (cwg) ? + v in + v in - output output v in + v in - note: the black areas of the output of the comparator represents the uncertainty due to input offsets and response time. note: to use cxin+ and cxinx- pins as analog input, the appropriate bits must be set in the ansel register and the correspond- ing tris bits must also be set to disable the output drivers. note 1: the cxoe bit of the cmxcon0 register overrides the port data latch. setting the cxon bit of the cmxcon0 register has no impact on the port override. 2: the internal output of the comparator is latched with each instruction cycle. unless otherwise specified, external outputs are not latched.
? 2011-2013 microchip technology inc. ds40001609b-page 153 pic16(l)f1508/9 17.2.5 comparator output polarity inverting the output of the comparator is functionally equivalent to swapping the comparator inputs. the polarity of the comparator output can be inverted by setting the cxpol bit of the cmxcon0 register. clearing the cxpol bit results in a non-inverted output. table 17-2 shows the output state versus input conditions, including polarity control. 17.2.6 comparator speed/power selection the trade-off between speed or power can be opti- mized during program execution with the cxsp control bit. the default state for this bit is ? 1 ? which selects the normal-speed mode. device power consumption can be optimized at the cost of slower comparator propaga- tion delay by clearing the cxsp bit to ? 0 ?. 17.3 analog input connection considerations a simplified circuit for an analog input is shown in figure 17-3 . since the analog input pins share their connection with a digital input, they have reverse biased esd protection diodes to v dd and v ss . the analog input, therefore, must be between v ss and v dd . if the input voltage deviates from this range by more than 0.6v in either direction, one of the diodes is for- ward biased and a latch-up may occur. a maximum source impedance of 10 k ? is recommended for the analog sources. also, any external component connected to an analog input pin, such as a capacitor or a zener diode, should have very little leakage current to minimize inaccuracies introduced. figure 17-3: analog input model table 17-2: comparator output state vs. input conditions input condition cxpol cxout cxv n > cxv p 00 cxv n < cxv p 01 cxv n > cxv p 11 cxv n < cxv p 10 note 1: when reading a port register, all pins configured as analog inputs will read as a ? 0 ?. pins configured as digital inputs will convert as an analog input, according to the input specification. 2: analog levels on any pin defined as a digital input, may cause the input buffer to consume more current than is specified. v a rs < 10k c pin 5 pf v dd v t ? 0.6v v t ? 0.6v r ic i leakage (1) vss legend: c pin = input capacitance i leakage = leakage current at the pin due to various junctions r ic = interconnect resistance r s = source impedance v a = analog voltage v t = threshold voltage to comparator note 1: see section 29.0 ?electrical specifications? . analog input pin
pic16(l)f1508/9 ds40001609b-page 154 ? 2011-2013 microchip technology inc. 17.4 comparator hysteresis a selectable amount of separation voltage can be added to the input pins of each comparator to provide a hysteresis function to the overall operation. hysteresis is enabled by setting the cxhys bit of the cmxcon0 register. see section 29.0 ?electrical specifications? for more information. 17.5 timer1 gate operation the output resulting from a comparator operation can be used as a source for gate control of timer1. see section 19.6 ?timer1 gate? for more information. this feature is useful for timing the duration or interval of an analog event. it is recommended that the comparator output be syn- chronized to timer1. this ensures that timer1 does not increment while a change in the comparator is occur- ring. 17.5.1 comparator output synchronization the output from the cx comparator can be synchronized with timer1 by setting the cxsync bit of the cmxcon0 register. once enabled, the comparator output is latched on the falling edge of the timer1 source clock. if a prescaler is used with timer1, the comparator output is latched after the prescaling function. to prevent a race condition, the comparator output is latched on the falling edge of the timer1 clock source and timer1 increments on the rising edge of its clock source. see the comparator block diagram ( figure 17-2 ) and the timer1 block diagram ( figure 19-1 ) for more information. 17.6 comparator interrupt an interrupt can be generated upon a change in the output value of the comparator for each comparator, a rising edge detector and a falling edge detector are present. when either edge detector is triggered and its associ- ated enable bit is set (cxintp and/or cxintn bits of the cmxcon1 register), the corresponding interrupt flag bit (cxif bit of the pir2 register) will be set. to enable the interrupt, you must set the following bits: ? cxon, cxpol and cxsp bits of the cmxcon0 register ? cxie bit of the pie2 register ? cxintp bit of the cmxcon1 register (for a rising edge detection) ? cxintn bit of the cmxcon1 register (for a falling edge detection) ? peie and gie bits of the intcon register the associated interrupt flag bit, cxif bit of the pir2 register, must be cleared in software. if another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 17.7 comparator response time the comparator output is indeterminate for a period of time after the change of an input source or the selection of a new reference voltage. this period is referred to as the response time. the response time of the comparator differs from the settling time of the voltage reference. therefore, both of these times must be considered when determining the total response time to a comparator input change. see the comparator and voltage refer- ence specifications in section 29.0 ?electrical specifi- cations? for more details. note: although a comparator is disabled, an interrupt can be generated by changing the output polarity with the cxpol bit of the cmxcon0 register, or by switching the comparator on or off with the cxon bit of the cmxcon0 register.
? 2011-2013 microchip technology inc. ds40001609b-page 155 pic16(l)f1508/9 17.8 register definitions: comparator control register 17-1: cmxcon0: comparator cx control register 0 r/w-0/0 r-0/0 r/w-0/0 r/w-0/0 u-0 r/w-1/1 r/w-0/0 r/w-0/0 cxon cxout cxoe cxpol ? cxsp cxhys cxsync bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 cxon: comparator enable bit 1 = comparator is enabled 0 = comparator is disabled and consumes no active power bit 6 cxout: comparator output bit if cxpol = 1 (inverted polarity): 1 = cxvp < cxvn 0 = cxvp > cxvn if cxpol = 0 (non-inverted polarity): 1 = cxvp > cxvn 0 = cxvp < cxvn bit 5 cxoe: comparator output enable bit 1 = cxout is present on the cxout pin. requires that the associated tris bit be cleared to actually drive the pin. not affected by cxon. 0 = cxout is internal only bit 4 cxpol: comparator output polarity select bit 1 = comparator output is inverted 0 = comparator output is not inverted bit 3 unimplemented: read as ? 0 ? bit 2 cxsp: comparator speed/power select bit 1 = comparator mode in normal-power, higher speed 0 = comparator mode in low-power, low-speed bit 1 cxhys: comparator hysteresis enable bit 1 = comparator hysteresis enabled 0 = comparator hysteresis disabled bit 0 cxsync: comparator output synchronous mode bit 1 = comparator output to timer1 and i/o pin is synchronous to changes on timer1 clock source. output updated on the falling edge of timer1 clock source. 0 = comparator output to timer1 and i/o pin is asynchronous
pic16(l)f1508/9 ds40001609b-page 156 ? 2011-2013 microchip technology inc. register 17-2: cmxcon1: comparator cx control register 1 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 cxintp cxintn cxpch<1:0> ? cxnch<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 cxintp: comparator interrupt on positive going edge enable bits 1 = the cxif interrupt flag will be set upon a positive going edge of the cxout bit 0 = no interrupt flag will be set on a positive going edge of the cxout bit bit 6 cxintn: comparator interrupt on negative going edge enable bits 1 = the cxif interrupt flag will be set upon a negative going edge of the cxout bit 0 = no interrupt flag will be set on a negative going edge of the cxout bit bit 5-4 cxpch<1:0>: comparator positive input channel select bits 11 = cxvp connects to v ss 10 = cxvp connects to fvr voltage reference 01 = cxvp connects to dac voltage reference 00 = cxvp connects to cxin+ pin bit 3 unimplemented: read as ? 0 ? bit 2-0 cxnch<2:0>: comparator negative input channel select bits 111 = reserved 110 = reserved 101 = reserved 100 = cxvn connects to fvr voltage reference 011 = cxvn connects to cxin3- pin 010 = cxvn connects to cxin2- pin 001 = cxvn connects to cxin1- pin 000 = cxvn connects to cxin0- pin register 17-3: cmout: comparator output register u-0 u-0 u-0 u-0 u-0 u-0 r-0/0 r-0/0 ? ? ? ? ? ? mc2out mc1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-2 unimplemented: read as ? 0 ? bit 1 mc2out: mirror copy of c2out bit bit 0 mc1out: mirror copy of c1out bit
? 2011-2013 microchip technology inc. ds40001609b-page 157 pic16(l)f1508/9 table 17-3: summary of registers as sociated with co mparator module name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 113 anselc ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 121 cm1con0 c1on c1out c1oe c1pol ? c1sp c1hys c1sync 155 cm2con0 c2on c2out c2oe c2pol ? c2sp c2hys c2sync 155 cm1con1 c1ntp c1intn c1pch<1:0> ? c1nch<2:0> 156 cm2con1 c2ntp c2intn c2pch<1:0> ? c2nch<2:0> 156 cmout ? ? ? ? ? ? mc2out mc1out 156 dac1con0 dacen ? dacoe1 dacoe2 ?dacpss ? ? 149 dac1con1 ? ? ? dacr<4:0> 149 fvrcon fvren fvrrdy tsen tsrng cdafvr<1:0> adfvr<1:0> 130 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 porta ? ? ra5 ra4 ra3 ra2 ra1 ra0 112 portc rc7 rc6 rc5 rc4 rc3 rc2 rc1 rc0 120 lata ? ? lata5 lata4 ? lata2 lata1 lata0 113 latc latc7 latc6 latc5 latc4 latc3 latc2 latc1 latc0 120 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are unused by the comparator module. note 1: unimplemented, read as ? 1 ?.
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? 2011-2013 microchip technology inc. ds40001609b-page 159 pic16(l)f1508/9 18.0 timer0 module the timer0 module is an 8-bit timer/counter with the following features: ? 8-bit timer/counter register (tmr0) ? 3-bit prescaler (independent of watchdog timer) ? programmable internal or external clock source ? programmable external clock edge selection ? interrupt on overflow ? tmr0 can be used to gate timer1 figure 18-1 is a block diagram of the timer0 module. 18.1 timer0 operation the timer0 module can be used as either an 8-bit timer or an 8-bit counter. 18.1.1 8-bit timer mode the timer0 module will increment every instruction cycle, if used without a prescaler. 8-bit timer mode is selected by clearing the tmr0cs bit of the option_reg register. when tmr0 is written, the increment is inhibited for two instruction cycles immediately following the write. 18.1.2 8-bit counter mode in 8-bit counter mode, the timer0 module will increment on every rising or falling edge of the t0cki pin. 8-bit counter mode using the t0cki pin is selected by setting the tmr0cs bit in the option_reg register to ? 1 ?. the rising or falling transition of the incrementing edge for either input source is determined by the tmr0se bit in the option_reg register. figure 18-1: timer0 block diagram note: the value written to the tmr0 register can be adjusted, in order to account for the two instruction cycle delay when tmr0 is written. tmr0se 0 1 fosc/4 prescaler t0_overflow r write to tmr0 set bit tmr0if t0cki sync circuit f osc /2 tmr0cs t0cki (1) note 1: the t0cki prescale output frequency should not exceed f osc /8. ps<2:0> 0 1 psa tmr0 q1 rev. 10-000017a_a1
pic16(l)f1508/9 ds40001609b-page 160 ? 2011-2013 microchip technology inc. 18.1.3 software programmable prescaler a software programmable prescaler is available for exclusive use with timer0. the prescaler is enabled by clearing the psa bit of the option_reg register. there are 8 prescaler options for the timer0 module ranging from 1:2 to 1:256. the prescale values are selectable via the ps<2:0> bits of the option_reg register. in order to have a 1:1 prescaler value for the timer0 module, the prescaler must be disabled by set- ting the psa bit of the option_reg register. the prescaler is not readable or writable. all instructions writing to the tmr0 register will clear the prescaler. 18.1.4 timer0 interrupt timer0 will generate an interrupt when the tmr0 register overflows from ffh to 00h. the tmr0if interrupt flag bit of the intcon register is set every time the tmr0 register overflows, regardless of whether or not the timer0 interrupt is enabled. the tmr0if bit can only be cleared in software. the timer0 interrupt enable is the tmr0ie bit of the intcon register. 18.1.5 8-bit counter mode synchronization when in 8-bit counter mode, the incrementing edge on the t0cki pin must be synchronized to the instruction clock. synchronization can be accomplished by sampling the prescaler output on the q2 and q4 cycles of the instruction clock. the high and low periods of the external clocking source must meet the timing requirements as shown in section 29.0 ?electrical specifications? . 18.1.6 operation during sleep timer0 cannot operate while the processor is in sleep mode. the contents of the tmr0 register will remain unchanged while the processor is in sleep mode. note: the watchdog timer (wdt) uses its own independent prescaler. note: the timer0 interrupt cannot wake the processor from sleep since the timer is frozen during sleep.
? 2011-2013 microchip technology inc. ds40001609b-page 161 pic16(l)f1508/9 18.2 register definitions: option register table 18-1: summary of registers associated with timer0 register 18-1: option_reg: option register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 wpuen intedg tmr0cs tmr0se psa ps<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 wpuen : weak pull-up enable bit 1 = all weak pull-ups are disabled (except mclr , if it is enabled) 0 = weak pull-ups are enabled by individual wpux latch values bit 6 intedg: interrupt edge select bit 1 = interrupt on rising edge of int pin 0 = interrupt on falling edge of int pin bit 5 tmr0cs: timer0 clock source select bit 1 = transition on t0cki pin 0 = internal instruction cycle clock (f osc /4) bit 4 tmr0se: timer0 source edge select bit 1 = increment on high-to-low transition on t0cki pin 0 = increment on low-to-high transition on t0cki pin bit 3 psa: prescaler assignment bit 1 = prescaler is not assigned to the timer0 module 0 = prescaler is assigned to the timer0 module bit 2-0 ps<2:0>: prescaler rate select bits name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page adcon2 trigsel<3:0> ? ? ? ? 141 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 option_reg wpuen intedg tmr0cs tmr0se psa ps<2:0> 161 tmr0 holding register for the 8-bit timer0 count 159 * trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the timer0 module. * page provides register information. note 1: unimplemented, read as ? 1 ?. 000 001 010 011 100 101 110 111 1 : 2 1 : 4 1 : 8 1 : 16 1 : 32 1 : 64 1 : 128 1 : 256 bit value timer0 rate
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? 2011-2013 microchip technology inc. ds40001609b-page 163 pic16(l)f1508/9 19.0 timer1 module with gate control the timer1 module is a 16-bit timer/counter with the following features: ? 16-bit timer/counter register pair (tmr1h:tmr1l) ? programmable internal or external clock source ? 2-bit prescaler ? optionally synchronized comparator out ? multiple timer1 gate (count enable) sources ? interrupt on overflow ? wake-up on overflow (external clock, asynchronous mode only) ? adc auto-conversion trigger(s) ? selectable gate source polarity ? gate toggle mode ? gate single-pulse mode ? gate value status ? gate event interrupt figure 19-1 is a block diagram of the timer1 module. figure 19-1: timer1 block diagram 00 11 10 01 t1g t0_overflow c1out_sync c2out_sync t1gss<1:0> t1gpol 0 1 single pulse acq. control 1 0 t1gspm dq tmr1on t1gtm set bit tmr1gif t1gval q1 tmr1ge tmr1on d q en tmr1l tmr1h t1_overflow set flag bit tmr1if tmr1 (2) 1 0 sosci/t1cki sosco t1oscen secondary oscillator out en 1 0 fosc internal clock fosc/4 internal clock lfintosc tmr1cs<1:0> 00 11 10 01 prescaler 1,2,4,8 to clock switching module t1sync sleep input fosc/2 internal clock t1ckps<1:0> synchronized clock input 2 det synchronize (3) 1: st buffer is high speed type when using t1cki. 2: timer1 register increments on rising edge. 3: synchronize does not operate while in sleep. (1) secondary clock d q ck r q note t1ggo/done t1clk det interrupt rev. 10-000018a_a0
pic16(l)f1508/9 ds40001609b-page 164 ? 2011-2013 microchip technology inc. 19.1 timer1 operation the timer1 module is a 16-bit incrementing counter which is accessed through the tmr1h:tmr1l register pair. writes to tmr1h or tmr1l directly update the counter. when used with an internal clock source, the module is a timer and increments on every instruction cycle. when used with an external clock source, the module can be used as either a timer or counter and incre- ments on every selected edge of the external source. timer1 is enabled by configuring the tmr1on and tmr1ge bits in the t1con and t1gcon registers, respectively. table 19-1 displays the timer1 enable selections. 19.2 clock source selection the tmr1cs<1:0> and t1oscen bits of the t1con register are used to select the clock source for timer1. table 19-2 displays the clock source selections. 19.2.1 internal clock source when the internal clock source is selected, the tmr1h:tmr1l register pair will increment on multiples of f osc as determined by the timer1 prescaler. when the f osc internal clock source is selected, the timer1 register value will in crement by four counts every instruction clock cycle. due to this condition, a 2 lsb error in resolution will occur when reading the timer1 value. to utilize the full resolution of timer1, an asynchronous input signal must be used to gate the timer1 clock input. the following asynchronous sources may be used: ? asynchronous event on the t1g pin to timer1 gate ? c1 or c2 comparator input to timer1 gate 19.2.2 external clock source when the external clock source is selected, the timer1 module may work as a timer or a counter. when enabled to count, timer1 is incremented on the rising edge of the external clock input t1cki. the external clock source can be synchronized to the microcontroller system clock or it can run asynchronously. table 19-1: timer1 enable selections tmr1on tmr1ge timer1 operation 00 off 01 off 10 always on 11 count enabled note: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: ? timer1 enabled after por ? write to tmr1h or tmr1l ? timer1 is disabled ? timer1 is disabled (tmr1on = 0 ) when t1cki is high then timer1 is enabled (tmr1on= 1 ) when t1cki is low. table 19-2: clock source selections tmr1cs<1:0> t1oscen clock source 11 x lfintosc 10 1 secondary oscillator circuit on sosci/sosco pins 0 external clocking on t1cki pin 01 x system clock (f osc ) 00 x instruction clock (f osc /4)
? 2011-2013 microchip technology inc. ds40001609b-page 165 pic16(l)f1508/9 19.3 timer1 prescaler timer1 has four prescaler options allowing 1, 2, 4 or 8 divisions of the clock input. the t1ckps bits of the t1con register control the prescale counter. the prescale counter is not directly readable or writable; however, the prescaler counter is cleared upon a write to tmr1h or tmr1l. 19.4 timer1 (secondary) oscillator a dedicated low-power 32.768 khz oscillator circuit is built-in between pins s1osi (input) and s1oso (ampli- fier output). this internal circuit is to be used in con- junction with an external 32.768 khz crystal. the oscillator circuit is enabled by setting the t1oscen bit of the t1con register. the oscillator will continue to run during sleep. 19.5 timer1 operation in asynchronous counter mode if control bit t1sync of the t1con register is set, the external clock input is not synchronized. the timer increments asynchronously to the internal phase clocks. if the external clock source is selected then the timer will continue to run during sleep and can generate an interrupt on overflow, which will wake-up the processor. however, special precautions in software are needed to read/write the timer (see section 19.5.1 ?reading and writing timer1 in asynchronous counter mode? ). 19.5.1 reading and writing timer1 in asynchronous counter mode reading tmr1h or tmr1l while the timer is running from an external asynchronous clock will ensure a valid read (taken care of in hardware). however, the user should keep in mind that reading the 16-bit timer in two 8-bit values itself, poses certain problems, since the timer may overflow between the reads. for writes, it is recommended that the user simply stop the timer and write the desired values. a write contention may occur by writing to the timer registers, while the register is incrementing. this may produce an unpredictable value in the tmr1h:tmr1l register pair. 19.6 timer1 gate timer1 can be configured to count freely or the count can be enabled and disabled using timer1 gate circuitry. this is also referred to as timer1 gate enable. timer1 gate can also be driven by multiple selectable sources. 19.6.1 timer1 gate enable the timer1 gate enable mode is enabled by setting the tmr1ge bit of the t1gcon register. the polarity of the timer1 gate enable mode is configured using the t1gpol bit of the t1gcon register. when timer1 gate enable mode is enabled, timer1 will increment on the rising edge of the timer1 clock source. when timer1 gate enable mode is disabled, no incrementing will occur and timer1 will hold the current count. see figure 19-3 for timing details. 19.6.2 timer1 gate source selection timer1 gate source selections are shown in table 19-4 . source selection is controlled by the t1gss<1:0> bits of the t1gcon register. the polarity for each available source is also selectable. polarity selection is controlled by the t1gpol bit of the t1gcon register. table 19-4: timer1 gate sources note: the oscillator requires some time to start-up and stabilize before use. the soscr bit in the oscstat register monitors the oscillator and indicates when the oscillator is ready for use. when t1oscen is set, the soscr bit is cleared. after 1024 cycles of the oscillator are countered, the soscr bit is set, indicating that the oscillator should be stable and ready for use. note: when switching from synchronous to asynchronous operation, it is possible to skip an increment. when switching from asynchronous to synchronous operation, it is possible to produce an additional increment. table 19-3: timer1 gate enable selections t1clk t1gpol t1g timer1 operation ? 00 counts ? 01 holds count ? 10 holds count ? 11 counts t1gss timer1 gate source 00 timer1 gate pin (t1g) 01 overflow of timer0 (t0_overflow) (tmr0 increments from ffh to 00h) 10 comparator 1 output (c1out_sync) (1) 11 comparator 2 output (c2out_sync) (1) note 1: optionally synchronized comparator output.
pic16(l)f1508/9 ds40001609b-page 166 ? 2011-2013 microchip technology inc. 19.6.2.1 t1g pin gate operation the t1g pin is one source for timer1 gate control. it can be used to supply an external source to the timer1 gate circuitry. 19.6.2.2 timer0 overflow gate operation when timer0 increments from ffh to 00h, a low-to- high pulse will automatically be generated and inter- nally supplied to the timer1 gate circuitry. 19.6.3 timer1 gate toggle mode when timer1 gate toggle mode is enabled, it is pos- sible to measure the full-cycle length of a timer1 gate signal, as opposed to the duration of a single level pulse. the timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. see figure 19-4 for timing details. timer1 gate toggle mode is enabled by setting the t1gtm bit of the t1gcon register. when the t1gtm bit is cleared, the flip-flop is cleared and held clear. this is necessary in order to control which edge is measured. 19.6.4 timer1 gate single-pulse mode when timer1 gate single-pulse mode is enabled, it is possible to capture a single pulse gate event. timer1 gate single-pulse mode is first enabled by setting the t1gspm bit in the t1gcon register. next, the t1ggo/ done bit in the t1gcon register must be set. the timer1 will be fully enabled on the next incrementing edge. on the next trailing edge of the pulse, the t1ggo/ done bit will automatically be cleared. no other gate events will be allowed to increment timer1 until the t1ggo/done bit is once again set in software. see figure 19-5 for timing details. if the single pulse gate mode is disabled by clearing the t1gspm bit in the t1gcon register, the t1ggo/done bit should also be cleared. enabling the toggle mode and the single-pulse mode simultaneously will permit both sections to work together. this allows the cycle times on the timer1 gate source to be measured. see figure 19-6 for timing details. 19.6.5 timer1 gate value status when timer1 gate value status is utilized, it is possi- ble to read the most current level of the gate control value. the value is stored in the t1gval bit in the t1gcon register. the t1gval bit is valid even when the timer1 gate is not enabled (tmr1ge bit is cleared). 19.6.6 timer1 gate event interrupt when timer1 gate event interrupt is enabled, it is pos- sible to generate an interrupt upon the completion of a gate event. when the falling edge of t1gval occurs, the tmr1gif flag bit in the pir1 register will be set. if the tmr1gie bit in the pie1 register is set, then an interrupt will be recognized. the tmr1gif flag bit operates even when the timer1 gate is not enabled (tmr1ge bit is cleared). note: enabling toggle mode at the same time as changing the gate polarity may result in indeterminate operation.
? 2011-2013 microchip technology inc. ds40001609b-page 167 pic16(l)f1508/9 19.7 timer1 interrupt the timer1 register pair (tmr1h:tmr1l) increments to ffffh and rolls over to 0000h. when timer1 rolls over, the timer1 interrupt flag bit of the pir1 register is set. to enable the interrupt on rollover, you must set these bits: ? tmr1on bit of the t1con register ? tmr1ie bit of the pie1 register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt is cleared by clearing the tmr1if bit in the interrupt service routine. 19.8 timer1 operation during sleep timer1 can only operate during sleep when setup in asynchronous counter mode. in this mode, an external crystal or clock source can be used to increment the counter. to set up the timer to wake the device: ? tmr1on bit of the t1con register must be set ? tmr1ie bit of the pie1 register must be set ? peie bit of the intcon register must be set ? t1sync bit of the t1con register must be set ? tmr1cs bits of the t1con register must be configured ? t1oscen bit of the t1con register must be configured the device will wake-up on an overflow and execute the next instructions. if the gie bit of the intcon register is set, the device will call the interrupt service routine. timer1 oscillator will continue to operate in sleep regardless of the t1sync bit setting. 19.8.1 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 11.1 ?alternate pin function? for more information. figure 19-2: timer1 incrementing edge note: the tmr1h:tmr1l register pair and the tmr1if bit should be cleared before enabling interrupts. t1cki = 1 when tmr1 enabled t1cki = 0 when tmr1 enabled note 1: arrows indicate counter increments. 2: in counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge of the clock.
pic16(l)f1508/9 ds40001609b-page 168 ? 2011-2013 microchip technology inc. figure 19-3: timer1 gate enable mode figure 19-4: timer1 gate toggle mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 tmr1ge t1gpol t1gtm t1g_in t1cki t1gval timer1 n n + 1 n + 2 n + 3 n + 4 n + 5 n + 6 n + 7 n + 8
? 2011-2013 microchip technology inc. ds40001609b-page 169 pic16(l)f1508/9 figure 19-5: timer1 gate single-pulse mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 n n + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif counting enabled on rising edge of t1g
pic16(l)f1508/9 ds40001609b-page 170 ? 2011-2013 microchip technology inc. figure 19-6: timer1 gate single-pulse and toggle combined mode tmr1ge t1gpol t1g_in t1cki t1gval timer1 nn + 1 n + 2 t1gspm t1ggo/ done set by software cleared by hardware on falling edge of t1gval set by hardware on falling edge of t1gval cleared by software cleared by software tmr1gif t1gtm counting enabled on rising edge of t1g n + 4 n + 3
? 2011-2013 microchip technology inc. ds40001609b-page 171 pic16(l)f1508/9 19.9 register definitions: timer1 control register 19-1: t1con: ti mer1 control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w-0/u u-0 r/w-0/u tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 tmr1cs<1:0>: timer1 clock source select bits 11 = timer1 clock source is lfintosc 10 = timer1 clock source is pin or oscillator: if t1oscen = 0 : external clock from t1cki pin (on the rising edge) if t1oscen = 1 : crystal oscillator on sosci/sosco pins 01 = timer1 clock source is system clock (f osc ) 00 = timer1 clock source is instruction clock (f osc /4) bit 5-4 t1ckps<1:0>: timer1 input clock prescale select bits 11 = 1:8 prescale value 10 = 1:4 prescale value 01 = 1:2 prescale value 00 = 1:1 prescale value bit 3 t1oscen: lp oscillator enable control bit 1 = secondary oscillator circuit enabled for timer1 0 = secondary oscillator circuit disabled for timer1 bit 2 t 1sync : timer1 synchronization control bit 1 = do not synchronize asynchronous clock input 0 = synchronize asynchronous clock input with system clock (f osc ) bit 1 unimplemented: read as ? 0 ? bit 0 tmr1on: timer1 on bit 1 = enables timer1 0 = stops timer1 and clears timer1 gate flip-flop
pic16(l)f1508/9 ds40001609b-page 172 ? 2011-2013 microchip technology inc. register 19-2: t1gcon: timer1 gate control register r/w-0/u r/w-0/u r/w-0/u r/w-0/u r/w/hc-0/u r-x/x r/w-0/u r/w-0/u tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = bit is cleared by hardware bit 7 tmr1ge: timer1 gate enable bit if tmr1on = 0 : this bit is ignored if tmr1on = 1 : 1 = timer1 counting is controlled by the timer1 gate function 0 = timer1 counts regardless of timer1 gate function bit 6 t1gpol: timer1 gate polarity bit 1 = timer1 gate is active-high (timer1 counts when gate is high) 0 = timer1 gate is active-low (timer1 counts when gate is low) bit 5 t1gtm: timer1 gate toggle mode bit 1 = timer1 gate toggle mode is enabled 0 = timer1 gate toggle mode is disabled and toggle flip-flop is cleared timer1 gate flip-flop toggles on every rising edge. bit 4 t1gspm: timer1 gate single-pulse mode bit 1 = timer1 gate single-pulse mode is enabled and is controlling timer1 gate 0 = timer1 gate single-pulse mode is disabled bit 3 t1ggo/done : timer1 gate single-pulse acquisition status bit 1 = timer1 gate single-pulse acquisition is ready, waiting for an edge 0 = timer1 gate single-pulse acquisition has completed or has not been started bit 2 t1gval: timer1 gate value status bit indicates the current state of the timer1 gate that could be provided to tmr1h:tmr1l. unaffected by timer1 gate enable (tmr1ge). bit 0 t1gss<1:0>: timer1 gate source select bits 11 = comparator 2 optionally synchronized output (c2out_sync) 10 = comparator 1 optionally synchronized output (c1out_sync) 01 = timer0 overflow output (t0_overflow) 00 = timer1 gate pin (t1g)
? 2011-2013 microchip technology inc. ds40001609b-page 173 pic16(l)f1508/9 table 19-5: summary of registers associated with timer1 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ?ansa4 ? ansa2 ansa1 ansa0 113 apfcon ? ? ? sssel t1gsel ? clc1sel nco1sel 110 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 oscstat soscr ? osts hfiofr ? ? lfiofr hfiofs 61 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 81 tmr1h holding register for the most significant byte of the 16-bit tmr1 count 167 * tmr1l holding register for the least significant byte of the 16-bit tmr1 count 167 * trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 t1con tmr1cs<1:0> t1ckps<1:0> t1oscen t1sync ?tmr1on 171 t1gcon tmr1ge t1gpol t1gtm t1gspm t1ggo/ done t1gval t1gss<1:0> 172 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the timer1 module. * page provides register information. note 1: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 174 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 175 pic16(l)f1508/9 20.0 timer2 module the timer2 module incorporates the following features: ? 8-bit timer and period registers (tmr2 and pr2, respectively) ? readable and writable (both registers) ? software programmable prescaler (1:1, 1:4, 1:16, and 1:64) ? software programmable postscaler (1:1 to 1:16) ? interrupt on tmr2 match with pr2 see figure 20-1 for a block diagram of timer2. figure 20-1: timer2 block diagram figure 20-2: timer2 timing diagram prescaler 1:1, 1:4, 1:16, 1:64 fosc/4 2 t2ckps<1:0> comparator postscaler 1:1 to 1:16 4 t2outps<3:0> set bit tmr2if tmr2 r pr2 t2_match to peripherals rev. 10-000019a_a0 0x03 0x00 0x01 0x02 0x03 0x00 0x01 0x02 1:4 pulse width (1) note 1: the pulse width of t2_match is equal to the scaled input of tmr2. f osc /4 prescale pr2 tmr2 t2_match rev. 10-000020a_a0
pic16(l)f1508/9 ds40001609b-page 176 ? 2011-2013 microchip technology inc. 20.1 timer2 operation the clock input to the timer2 module is the system instruction clock (f osc /4). tmr2 increments from 00h on each clock edge. a 4-bit counter/prescaler on the clock input allows direct input, divide-by-4 and divide-by-16 prescale options. these options are selected by the prescaler control bits, t2ckps<1:0> of the t2con register. the value of tmr2 is compared to that of the period register, pr2, on each clock cycle. when the two values match, the comparator generates a match signal as the timer output. this signal also resets the value of tmr2 to 00h on the next cycle and drives the output counter/ postscaler (see section 20.2 ?timer2 interrupt? ). the tmr2 and pr2 registers are both directly readable and writable. the tmr2 register is cleared on any device reset, whereas the pr2 register initializes to ffh. both the prescaler and postscaler counters are cleared on the following events: ? a write to the tmr2 register ? a write to the t2con register ? power-on reset (por) ? brown-out reset (bor) ?mclr reset ? watchdog timer (wdt) reset ? stack overflow reset ? stack underflow reset ? reset instruction 20.2 timer2 interrupt timer2 can also generate an optional device interrupt. the timer2 output signal (t2_match) provides the input for the 4-bit counter/postscaler. this counter generates the tmr2 match interrupt flag which is latched in tmr2if of the pir1 register. the interrupt is enabled by setting the tmr2 match interrupt enable bit, tmr2ie of the pie1 register. a range of 16 postscale options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, t2outps<3:0>, of the t2con register. 20.3 timer2 output the output of tmr2 is t2_match. t2_match is available to the following peripherals: ? configurable logic cell (clc) ? master synchronous serial port (mssp) ? numerically controlled oscillator (nco) ? pulse width modulator (pwm) the t2_match signal is synchronous with the system clock. figure 20-3 shows two examples of the timing of the t2_match signal relative to f osc and prescale value, t2ckps<1:0>. the upper diagram illustrates 1:1 prescale timing and the lower diagram, 1:x prescale timing. figure 20-3: t2_match timing diagram 20.4 timer2 operation during sleep timer2 cannot be operated while the processor is in sleep mode. the contents of the tmr2 and pr2 registers will remain unchanged while the processor is in sleep mode. note: tmr2 is not cleared when t2con is written. t2_match f osc /4 tmr2 = pr2 match tmr2 = 0 ... prescale = 1:x (t2ckps< 1:0 > = 01,10,11 ) t cy 1t cy 2t cy x ... ... q1 q2 q3 f osc tmr2 = pr2 match tmr2 = 0 q1 q4 t2_match f osc /4 prescale = 1:1 (t2ckps< 1:0 > = 00 ) t cy 1 rev. 10-000021a_a1
? 2011-2013 microchip technology inc. ds40001609b-page 177 pic16(l)f1508/9 20.5 register definitions: timer2 control table 20-1: summary of registers associated with timer2 register 20-1: t2con: ti mer2 control register u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? t2outps<3:0> tmr2on t2ckps<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-3 t2outps<3:0>: timer2 output postscaler select bits 0000 = 1:1 postscaler 0001 = 1:2 postscaler 0010 = 1:3 postscaler 0011 = 1:4 postscaler 0100 = 1:5 postscaler 0101 = 1:6 postscaler 0110 = 1:7 postscaler 0111 = 1:8 postscaler 1000 = 1:9 postscaler 1001 = 1:10 postscaler 1010 = 1:11 postscaler 1011 = 1:12 postscaler 1100 = 1:13 postscaler 1101 = 1:14 postscaler 1110 = 1:15 postscaler 1111 = 1:16 postscaler bit 2 tmr2on: timer2 on bit 1 = timer2 is on 0 = timer2 is off bit 1-0 t2ckps<1:0>: timer2 clock prescale select bits 00 = prescaler is 1 01 = prescaler is 4 10 = prescaler is 16 11 = prescaler is 64 name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ?tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 pr2 timer2 module period register 175 * t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 177 tmr2 holding register for the 8-bit tmr2 count 175 * legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for timer2 module. * page provides register information.
pic16(l)f1508/9 ds40001609b-page 178 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 179 pic16(l)f1508/9 21.0 master synchronous serial port (mssp) module 21.1 mssp module overview the master synchronous serial port (msspx) module is a serial interface useful for communicating with other peripheral or microcontroller devices. these peripheral devices may be serial eeproms, shift registers, dis- play drivers, a/d converters, etc. the msspx module can operate in one of two modes: ? serial peripheral interface (spi) ? inter-integrated circuit (i 2 c?) the spi interface supports the following modes and features: ?master mode ? slave mode ? clock parity ? slave select synchronization (slave mode only) ? daisy-chain connection of slave devices figure 21-1 is a block diagram of the spi interface module. figure 21-1: mssp block diagram (spi mode) ( ) read write data bus sspsr reg sspm<3:0> bit 0 shift clock ssx control enable edge select clock select t2_match t osc prescaler 4, 16, 64 2 edge select 2 (ckp, cke) 4 tris bit sdo sspbuf reg sdi ss sck baud rate generator (sspxadd) sdo_out sck_out
pic16(l)f1508/9 ds40001609b-page 180 ? 2011-2013 microchip technology inc. the i 2 c interface supports the following modes and features: ?master mode ? slave mode ? byte nacking (slave mode) ? limited multi-master support ? 7-bit and 10-bit addressing ? start and stop interrupts ? interrupt masking ? clock stretching ? bus collision detection ? general call address matching ?address masking ? address hold and data hold modes ? selectable sdax hold times figure 21-2 is a block diagram of the i 2 c interface mod- ule in master mode. figure 21-3 is a diagram of the i 2 c interface module in slave mode. the pic16f1508/9 has one mssp module. figure 21-2: msspx block diagram (i 2 c? master mode) note 1: in devices with more than one mssp module, it is very important to pay close attention to sspxconx register names. sspxcon1 and sspxcon2 registers control different operational aspects of the same module, while sspxcon1 and ssp2con1 control the same features for two different modules. 2: throughout this section, generic refer- ences to an msspx module in any of its operating modes may be interpreted as being equally applicable to msspx or mssp2. register names, module i/o sig- nals, and bit names may use the generic designator ?x? to indicate the use of a numeral to distinguish a particular module when required. read write sspxsr start bit, stop bit, start bit detect, sspxbuf internal data bus set/reset: s, p, sspxstat, wcol, sspov shift clock msb lsb sdax acknowledge generate (sspxcon2) stop bit detect write collision detect clock arbitration state counter for end of xmit/rcv sclx sclx in bus collision sdax in receive enable (rcen) clock cntl clock arbitrate/bcol detect (hold off clock source) [sspm<3:0>] baud rate reset sen, pen (sspxcon2) generator (sspxadd) address match detect set sspxif, bclxif
? 2011-2013 microchip technology inc. ds40001609b-page 181 pic16(l)f1508/9 figure 21-3: mssp block diagram (i 2 c? slave mode) read write sspxsr reg match detect sspxadd reg start and stop bit detect sspxbuf reg internal data bus addr match set, reset s, p bits (sspxstat reg) sclx sdax shift clock msb lsb sspxmsk reg
pic16(l)f1508/9 ds40001609b-page 182 ? 2011-2013 microchip technology inc. 21.2 spi mode overview the serial peripheral interface (spi) bus is a synchronous serial data communication bus that operates in full-duplex mode. devices communicate in a master/slave environment where the master device initiates the communication. a slave device is controlled through a chip select known as slave select. the spi bus specifies four signal connections: ? serial clock (sckx) ? serial data out (sdox) ? serial data in (sdix) ? slave select (ssx ) figure 21-1 shows the block diagram of the mssp module when operating in spi mode. the spi bus operates with a single master device and one or more slave devices. when multiple slave devices are used, an independent slave select con- nection is required from the master device to each slave device. figure 21-4 shows a typical connection between a master device and multiple slave devices. the master selects only one slave at a time. most slave devices have tri-state outputs so their output signal appears disconnected from the bus when they are not selected. transmissions involve two shift registers, eight bits in size, one in the master and one in the slave. with either the master or the slave device, data is always shifted out one bit at a time, with the most significant bit (msb) shifted out first. at the same time, a new least significant bit (lsb) is shifted into the same register. figure 21-5 shows a typical connection between two processors configured as master and slave devices. data is shifted out of both shift registers on the pro- grammed clock edge and latched on the opposite edge of the clock. the master device transmits information out on its sdox output pin which is connected to, and received by, the slave?s sdix input pin. the slave device trans- mits information out on its sdox output pin, which is connected to, and received by, the master?s sdix input pin. to begin communication, the master device first sends out the clock signal. both the master and the slave devices should be configured for the same clock polar- ity. the master device starts a transmission by sending out the msb from its shift register. the slave device reads this bit from that same line and saves it into the lsb position of its shift register. during each spi clock cycle, a full-duplex data transmission occurs. this means that while the master device is sending out the msb from its shift register (on its sdox pin) and the slave device is reading this bit and saving it as the lsb of its shift register, that the slave device is also sending out the msb from its shift register (on its sdox pin) and the master device is reading this bit and saving it as the lsb of its shift register. after eight bits have been shifted out, the master and slave have exchanged register values. if there is more data to exchange, the shift registers are loaded with new data and the process repeats itself. whether the data is meaningful or not (dummy data), depends on the application software. this leads to three scenarios for data transmission: ? master sends useful data and slave sends dummy data. ? master sends useful data and slave sends useful data. ? master sends dummy data and slave sends use- ful data. transmissions may involve any number of clock cycles. when there is no more data to be transmitted, the master stops sending the clock signal and it dese- lects the slave. every slave device connected to the bus that has not been selected through its slave select line must disre- gard the clock and transmission signals and must not transmit out any data of its own.
? 2011-2013 microchip technology inc. ds40001609b-page 183 pic16(l)f1508/9 figure 21-4: spi master and multiple slave connection 21.2.1 spi mode registers the mssp module has five registers for spi mode operation. these are: ? mssp status register (sspxstat) ? mssp control register 1 (sspxcon1) ? mssp control register 3 (sspxcon3) ? mssp data buffer register (sspxbuf) ? mssp address register (sspxadd) ? mssp shift register (sspxsr) (not directly accessible) sspxcon1 and sspxstat are the control and status registers in spi mode operation. the sspxcon1 register is readable and writable. the lower six bits of the sspxstat are read-only. the upper two bits of the sspxstat are read/write. in spi master mode, sspxadd can be loaded with a value used in the baud rate generator. more informa- tion on the baud rate generator is available in section 21.7 ?baud rate generator? . sspxsr is the shift register used for shifting data in and out. sspxbuf provides indirect access to the sspxsr register. sspxbuf is the buffer register to which data bytes are written, and from which data bytes are read. in receive operations, sspxsr and sspxbuf together create a buffered receiver. when sspxsr receives a complete byte, it is transferred to sspxbuf and the sspxif interrupt is set. during transmission, the sspxbuf is not buffered. a write to sspxbuf will write to both sspxbuf and sspxsr. spi master sckx sdox sdix general i/o general i/o general i/o sckx sdix sdox ssx spi slave #1 sckx sdix sdox ssx spi slave #2 sckx sdix sdox ssx spi slave #3
pic16(l)f1508/9 ds40001609b-page 184 ? 2011-2013 microchip technology inc. 21.2.2 spi mode operation when initializing the spi, several options need to be specified. this is done by programming the appropriate control bits (sspxcon1<5:0> and sspxstat<7:6>). these control bits allow the following to be specified: ? master mode (sckx is the clock output) ? slave mode (sckx is the clock input) ? clock polarity (idle state of sckx) ? data input sample phase (middle or end of data output time) ? clock edge (output data on rising/falling edge of sckx) ? clock rate (master mode only) ? slave select mode (slave mode only) to enable the serial port, ssp enable bit, sspen of the sspxcon1 register, must be set. to reset or reconfigure spi mode, clear the sspen bit, re-initialize the sspxconx registers and then set the sspen bit. this configures the sdi, sdo, sck and ss pins as serial port pins. for the pins to behave as the serial port function, some must have their data direction bits (in the tris register) appropriately programmed as follows: ? sdix must have corresponding tris bit set ? sdox must have corresponding tris bit cleared ? sckx (master mode) must have corresponding tris bit cleared ? sckx (slave mode) must have corresponding tris bit set ? ssx must have corresponding tris bit set any serial port function that is not desired may be overridden by programming the corresponding data direction (tris) register to the opposite value. the mssp consists of a transmit/receive shift register (sspxsr) and a buffer register (sspxbuf). the sspxsr shifts the data in and out of the device, msb first. the sspxbuf holds the data that was written to the sspxsr until the received data is ready. once the eight bits of data have been received, that byte is moved to the sspxbuf register. then, the buffer full detect bit, bf of the sspxstat register, and the interrupt flag bit, sspxif, are set. this double-buffering of the received data (sspxbuf) allows the next byte to start reception before reading the data that was just received. any write to the sspxbuf register during transmission/reception of data will be ignored and the write collision detect bit, wcol of the sspxcon1 register, will be set. user software must clear the wcol bit to allow the following write(s) to the sspxbuf register to complete successfully. when the application software is expecting to receive valid data, the sspxbuf should be read before the next byte of data to transfer is written to the sspxbuf. the buffer full bit, bf of the sspxstat register, indi- cates when sspxbuf has been loaded with the received data (transmission is complete). when the sspxbuf is read, the bf bit is cleared. this data may be irrelevant if the spi is only a transmitter. generally, the mssp interrupt is used to determine when the transmission/reception has completed. if the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. the sspxsr is not directly readable or writable and can only be accessed by addressing the sspxbuf register. additionally, the sspxstat register indicates the various status conditions.
? 2011-2013 microchip technology inc. ds40001609b-page 185 pic16(l)f1508/9 figure 21-5: spi mast er/slave connection serial input buffer (buf) shift register (sspxsr) msb lsb sdox sdix processor 1 sckx spi master sspm<3:0> = 00xx serial input buffer (sspxbuf) shift register (sspxsr) lsb msb sdix sdox processor 2 sckx spi slave sspm<3:0> = 010x serial clock ssx slave select general i/o (optional) = 1010
pic16(l)f1508/9 ds40001609b-page 186 ? 2011-2013 microchip technology inc. 21.2.3 spi master mode the master can initiate the data transfer at any time because it controls the sckx line. the master determines when the slave (processor 2, figure 21-5 ) is to broadcast data by the software protocol. in master mode, the data is transmitted/received as soon as the sspxbuf register is written to. if the spi is only going to receive, the sdox output could be dis- abled (programmed as an input). the sspxsr register will continue to shift in the signal present on the sdix pin at the programmed clock rate. as each byte is received, it will be loaded into the sspxbuf register as if a normal received byte (interrupts and status bits appropriately set). the clock polarity is selected by appropriately programming the ckp bit of the sspxcon1 register and the cke bit of the sspxstat register. this then, would give waveforms for spi communication as shown in figure 21-6 , figure 21-8 , figure 21-9 and figure 21-10 , where the msb is transmitted first. in master mode, the spi clock rate (bit rate) is user programmable to be one of the following: ?f osc /4 (or t cy ) ?f osc /16 (or 4 * t cy ) ?f osc /64 (or 16 * t cy ) ? timer2 output/2 ? fosc/(4 * (sspxadd + 1)) figure 21-6 shows the waveforms for master mode. when the cke bit is set, the sdox data is valid before there is a clock edge on sckx. the change of the input sample is shown based on the state of the smp bit. the time when the sspxbuf is loaded with the received data is shown. figure 21-6: spi mode waveform (master mode) sckx (ckp = 0 sckx (ckp = 1 sckx (ckp = 0 sckx (ckp = 1 4 clock modes input sample input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 sdix sspxif (smp = 1 ) (smp = 0 ) (smp = 1 ) cke = 1 ) cke = 0 ) cke = 1 ) cke = 0 ) (smp = 0 ) write to sspxbuf sspxsr to sspxbuf sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 (cke = 0 ) (cke = 1 ) bit 0
? 2011-2013 microchip technology inc. ds40001609b-page 187 pic16(l)f1508/9 21.2.4 spi slave mode in slave mode, the data is transmitted and received as external clock pulses appear on sckx. when the last bit is latched, the sspxif interrupt flag bit is set. before enabling the module in spi slave mode, the clock line must match the proper idle state. the clock line can be observed by reading the sckx pin. the idle state is determined by the ckp bit of the sspxcon1 register. while in slave mode, the external clock is supplied by the external clock source on the sckx pin. this exter- nal clock must meet the minimum high and low times as specified in the electrical specifications. while in sleep mode, the slave can transmit/receive data. the shift register is clocked from the sckx pin input and when a byte is received, the device will gen- erate an interrupt. if enabled, the device will wake-up from sleep. 21.2.4.1 daisy-chain configuration the spi bus can sometimes be connected in a daisy-chain configuration. the first slave output is con- nected to the second slave input, the second slave output is connected to the third slave input, and so on. the final slave output is connected to the master input. each slave sends out, during a second group of clock pulses, an exact copy of what was received during the first group of clock pulses. the whole chain acts as one large communication shift register. the daisy-chain feature only requires a single slave select line from the master device. figure 21-7 shows the block diagram of a typical daisy-chain connection when operating in spi mode. in a daisy-chain configuration, only the most recent byte on the bus is required by the slave. setting the boen bit of the sspxcon3 register will enable writes to the sspxbuf register, even if the previous byte has not been read. this allows the software to ignore data that may not apply to it. 21.2.5 slave select synchronization the slave select can also be used to synchronize com- munication. the slave select line is held high until the master device is ready to communicate. when the slave select line is pulled low, the slave knows that a new transmission is starting. if the slave fails to receive the communication properly, it will be reset at the end of the transmission, when the slave select line returns to a high state. the slave is then ready to receive a new transmission when the slave select line is pulled low again. if the slave select line is not used, there is a risk that the slave will even- tually become out of sync with the master. if the slave misses a bit, it will always be one bit off in future trans- missions. use of the slave select line allows the slave and master to align themselves at the beginning of each transmission. the ssx pin allows a synchronous slave mode. the spi must be in slave mode with ssx pin control enabled (sspxcon1<3:0> = 0100 ). when the ssx pin is low, transmission and reception are enabled and the sdox pin is driven. when the ssx pin goes high, the sdox pin is no longer driven, even if in the middle of a transmitted byte and becomes a floating output. external pull-up/pull-down resistors may be desirable depending on the applica- tion. when the spi module resets, the bit counter is forced to ? 0 ?. this can be done by either forcing the ssx pin to a high level or clearing the sspen bit. note 1: when the spi is in slave mode with ssx pin control enabled (sspxcon1<3:0> = 0100 ), the spi module will reset if the ssx pin is set to v dd . 2: when the spi is used in slave mode with cke set; the user must enable ssx pin control. 3: while operated in spi slave mode the smp bit of the sspxstat register must remain clear.
pic16(l)f1508/9 ds40001609b-page 188 ? 2011-2013 microchip technology inc. figure 21-7: spi daisy-chain connection figure 21-8: slave select synchronous waveform spi master sck sdox sdix general i/o sck sdix sdox ssx spi slave #1 sck sdix sdox ssx spi slave #2 sck sdix sdox ssx spi slave #3 sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 7 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag bit 0 bit 7 bit 0 bit 6 sspxbuf to sspxsr shift register sspxsr and bit count are reset
? 2011-2013 microchip technology inc. ds40001609b-page 189 pic16(l)f1508/9 figure 21-9: spi mode wavefo rm (slave mode with cke = 0 ) figure 21-10: spi mode waveform (slave mode with cke = 1 ) sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 0 ) cke = 0 ) write to sspxbuf sspxsr to sspxbuf ssx flag optional bit 0 detection active write collision valid sckx (ckp = 1 sckx (ckp = 0 input sample sdix bit 7 bit 0 sdox bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sspxif interrupt cke = 1 ) cke = 1 ) write to sspxbuf sspxsr to sspxbuf ssx flag not optional write collision detection active valid
pic16(l)f1508/9 ds40001609b-page 190 ? 2011-2013 microchip technology inc. 21.2.6 spi operation in sleep mode in spi master mode, module clocks may be operating at a different speed than when in full-power mode; in the case of the sleep mode, all clocks are halted. special care must be taken by the user when the mssp clock is much faster than the system clock. in slave mode, when mssp interrupts are enabled, after the master completes sending data, an mssp interrupt will wake the controller from sleep. if an exit from sleep mode is not desired, mssp inter- rupts should be disabled. in spi master mode, when the sleep mode is selected, all module clocks are halted and the transmis- sion/reception will remain in that state until the device wakes. after the device returns to run mode, the mod- ule will resume transmitting and receiving data. in spi slave mode, the spi transmit/receive shift register operates asynchronously to the device. this allows the device to be placed in sleep mode and data to be shifted into the spi transmit/receive shift register. when all eight bits have been received, the mssp interrupt flag bit will be set and if enabled, will wake the device. table 21-1: summary of registers as sociated with spi operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 113 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 ssp1buf synchronous serial port receive buffer/transmit register 183 * ssp1con1 wcol sspov sspen ckp sspm<3:0> 230 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 232 ssp1stat smp cke d/a p s r/w ua bf 228 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp in spi mode. * page provides register information. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 191 pic16(l)f1508/9 21.3 i 2 c mode overview the inter-integrated circuit bus (i 2 c) is a multi-master serial data communication bus. devices communicate in a master/slave environment where the master devices initiate the communication. a slave device is controlled through addressing. the i 2 c bus specifies two signal connections: ? serial clock (sclx) ? serial data (sdax) figure 21-2 and figure 21-3 show the block diagrams of the mssp module when operating in i 2 c mode. both the sclx and sdax connections are bidirectional open-drain lines, each requiring pull-up resistors for the supply voltage. pulling the line to ground is considered a logical zero and letting the line float is considered a logical one. figure 21-11 shows a typical connection between two processors configured as master and slave devices. the i 2 c bus can operate with one or more master devices and one or more slave devices. there are four potential modes of operation for a given device: ? master transmit mode (master is transmitting data to a slave) ? master receive mode (master is receiving data from a slave) ?slave transmit mode (slave is transmitting data to a master) ? slave receive mode (slave is receiving data from the master) to begin communication, a master device starts out in master transmit mode. the master device sends out a start bit followed by the address byte of the slave it intends to communicate with. this is followed by a sin- gle read/write bit, which determines whether the mas- ter intends to transmit to or receive data from the slave device. if the requested slave exists on the bus, it will respond with an acknowledge bit, otherwise known as an ack . the master then continues in either transmit mode or receive mode and the slave continues in the comple- ment, either in receive mode or transmit mode, respectively. a start bit is indicated by a high-to-low transition of the sdax line while the sclx line is held high. address and data bytes are sent out, most significant bit (msb) first. the read/write bit is sent out as a logical one when the master intends to read data from the slave, and is sent out as a logical zero when it intends to write data to the slave. figure 21-11: i 2 c master/ slave connection the acknowledge bit (ack ) is an active-low signal, which holds the sdax line low to indicate to the trans- mitter that the slave device has received the transmit- ted data and is ready to receive more. the transition of a data bit is always performed while the sclx line is held low. transitions that occur while the sclx line is held high are used to indicate start and stop bits. if the master intends to write to the slave, then it repeat- edly sends out a byte of data, with the slave responding after each byte with an ack bit. in this example, the master device is in master transmit mode and the slave is in slave receive mode. if the master intends to read from the slave, then it repeatedly receives a byte of data from the slave, and responds after each byte with an ack bit. in this exam- ple, the master device is in master receive mode and the slave is slave transmit mode. on the last byte of data communicated, the master device may end the transmission by sending a stop bit. if the master device is in receive mode, it sends the stop bit in place of the last ack bit. a stop bit is indi- cated by a low-to-high transition of the sdax line while the sclx line is held high. in some cases, the master may want to maintain con- trol of the bus and re-initiate another transmission. if so, the master device may send another start bit in place of the stop bit or last ack bit when it is in receive mode. the i 2 c bus specifies three message protocols; ? single message where a master writes data to a slave. ? single message where a master reads data from a slave. ? combined message where a master initiates a minimum of two writes, or two reads, or a combination of writes and reads, to one or more slaves. master sclx sdax sclx sdax slave v dd v dd
pic16(l)f1508/9 ds40001609b-page 192 ? 2011-2013 microchip technology inc. when one device is transmitting a logical one, or letting the line float, and a second device is transmitting a log- ical zero, or holding the line low, the first device can detect that the line is not a logical one. this detection, when used on the sclx line, is called clock stretching. clock stretching gives slave devices a mechanism to control the flow of data. when this detection is used on the sdax line, it is called arbitration. arbitration ensures that there is only one master device communi- cating at any single time. 21.3.1 clock stretching when a slave device has not completed processing data, it can delay the transfer of more data through the process of clock stretching. an addressed slave device may hold the sclx clock line low after receiving or sending a bit, indicating that it is not yet ready to con- tinue. the master that is communicating with the slave will attempt to raise the sclx line in order to transfer the next bit, but will detect that the clock line has not yet been released. because the sclx connection is open-drain, the slave has the ability to hold that line low until it is ready to continue communicating. clock stretching allows receivers that cannot keep up with a transmitter to control the flow of incoming data. 21.3.2 arbitration each master device must monitor the bus for start and stop bits. if the device detects that the bus is busy, it cannot begin a new message until the bus returns to an idle state. however, two master devices may try to initiate a trans- mission on or about the same time. when this occurs, the process of arbitration begins. each transmitter checks the level of the sdax data line and compares it to the level that it expects to find. the first transmitter to observe that the two levels do not match, loses arbitra- tion, and must stop transmitting on the sdax line. for example, if one transmitter holds the sdax line to a logical one (lets it float) and a second transmitter holds it to a logical zero (pulls it low), the result is that the sdax line will be low. the first transmitter then observes that the level of the line is different than expected and concludes that another transmitter is communicating. the first transmitter to notice this difference is the one that loses arbitration and must stop driving the sdax line. if this transmitter is also a master device, it also must stop driving the sclx line. it then can monitor the lines for a stop condition before trying to reissue its transmission. in the meantime, the other device that has not noticed any difference between the expected and actual levels on the sdax line continues with its original transmission. it can do so without any compli- cations, because so far, the transmission appears exactly as expected with no other transmitter disturbing the message. slave transmit mode can also be arbitrated, when a master addresses multiple slaves, but this is less com- mon. if two master devices are sending a message to two dif- ferent slave devices at the address stage, the master sending the lower slave address always wins arbitra- tion. when two master devices send messages to the same slave address, and addresses can sometimes refer to multiple slaves, the arbitration process must continue into the data stage. arbitration usually occurs very rarely, but it is a neces- sary process for proper multi-master support.
? 2011-2013 microchip technology inc. ds40001609b-page 193 pic16(l)f1508/9 21.4 i 2 c mode operation all mssp i 2 c communication is byte oriented and shifted out msb first. six sfr registers and two interrupt flags interface the module with the pic ? microcontroller and user software. two pins, sdax and sclx, are exercised by the module to communi- cate with other external i 2 c devices. 21.4.1 byte format all communication in i 2 c is done in 9-bit segments. a byte is sent from a master to a slave or vice-versa, followed by an acknowledge bit sent back. after the eighth falling edge of the sclx line, the device output- ting data on the sdax changes that pin to an input and reads in an acknowledge value on the next clock pulse. the clock signal, sclx, is provided by the master. data is valid to change while the sclx signal is low, and sampled on the rising edge of the clock. changes on the sdax line while the sclx line is high define special conditions on the bus, explained below. 21.4.2 definition of i 2 c terminology there is language and terminology in the description of i 2 c communication that have definitions specific to i 2 c. that word usage is defined below and may be used in the rest of this document without explanation. this table was adapted from the philips i 2 c tm specification. 21.4.3 sdax and sclx pins selection of any i 2 c mode with the sspen bit set, forces the sclx and sdax pins to be open-drain. these pins should be set by the user to inputs by set- ting the appropriate tris bits. 21.4.4 sdax hold time the hold time of the sdax pin is selected by the sdaht bit of the sspxcon3 register. hold time is the time sdax is held valid after the falling edge of sclx. setting the sdaht bit selects a longer 300 ns mini- mum hold time and may help on buses with large capacitance. table 21-2: i 2 c bus terms note: data is tied to output zero when an i 2 c mode is enabled. term description transmitter the device which shifts data out onto the bus. receiver the device which shifts data in from the bus. master the device that initiates a transfer, generates clock signals and termi- nates a transfer. slave the device addressed by the master. multi-master a bus with more than one device that can initiate data transfers. arbitration procedure to ensure that only one master at a time controls the bus. winning arbitration ensures that the message is not corrupted. synchronization procedure to synchronize the clocks of two or more devices on the bus. idle no master is controlling the bus, and both sdax and sclx lines are high. active any time one or more master devices are controlling the bus. addressed slave slave device that has received a matching address and is actively being clocked by a master. matching address address byte that is clocked into a slave that matches the value stored in sspxadd. write request slave receives a matching address with r/w bit clear, and is ready to clock in data. read request master sends an address byte with the r/w bit set, indicating that it wishes to clock data out of the slave. this data is the next and all following bytes until a restart or stop. clock stretching when a device on the bus hold sclx low to stall communication. bus collision any time the sdax line is sampled low by the module while it is out- putting and expected high state.
pic16(l)f1508/9 ds40001609b-page 194 ? 2011-2013 microchip technology inc. 21.4.5 start condition the i 2 c specification defines a start condition as a transition of sdax from a high to a low state while sclx line is high. a start condition is always gener- ated by the master and signifies the transition of the bus from an idle to an active state. figure 21-12 shows wave forms for start and stop conditions. a bus collision can occur on a start condition if the module samples the sdax line low before asserting it low. this does not conform to the i 2 c specification that states no bus collision can occur on a start. 21.4.6 stop condition a stop condition is a transition of the sdax line from low-to-high state while the sclx line is high. 21.4.7 restart condition a restart is valid any time that a stop would be valid. a master can issue a restart if it wishes to hold the bus after terminating the current transfer. a restart has the same effect on the slave that a start would, resetting all slave logic and preparing it to clock in an address. the master may want to address the same or another slave. figure 21-13 shows the wave form for a restart condition. in 10-bit addressing slave mode a restart is required for the master to clock data out of the addressed slave. once a slave has been fully addressed, match- ing both high and low address bytes, the master can issue a restart and the high address byte with the r/w bit set. the slave logic will then hold the clock and prepare to clock out data. after a full match with r/w clear in 10-bit mode, a prior match flag is set and maintained. until a stop condi- tion, a high address with r/w clear, or high address match fails. 21.4.8 start/stop condition interrupt masking the scie and pcie bits of the sspxcon3 register can enable the generation of an interrupt in slave modes that do not typically support this function. slave modes where interrupt on start and stop detect are already enabled, these bits will have no effect. figure 21-12: i 2 c start and stop conditions figure 21-13: i 2 c restart condition note: at least one sclx low time must appear before a stop is valid, therefore, if the sdax line goes low then high again while the sclx line stays high, only the start condition is detected. sdax sclx p stop condition s start condition change of data allowed change of data allowed restart condition sr change of data allowed change of data allowed
? 2011-2013 microchip technology inc. ds40001609b-page 195 pic16(l)f1508/9 21.4.9 acknowledge sequence the ninth sclx pulse for any transferred byte in i 2 c is dedicated as an acknowledge. it allows receiving devices to respond back to the transmitter by pulling the sdax line low. the transmitter must release con- trol of the line during this time to shift in the response. the acknowledge (ack ) is an active-low signal, pull- ing the sdax line low indicated to the transmitter that the device has received the transmitted data and is ready to receive more. the result of an ack is placed in the ackstat bit of the sspxcon2 register. slave software, when the ahen and dhen bits are set, allow the user to set the ack value sent back to the transmitter. the ackdt bit of the sspxcon2 reg- ister is set/cleared to determine the response. slave hardware will generate an ack response if the ahen and dhen bits of the sspxcon3 register are clear. there are certain conditions where an ack will not be sent by the slave. if the bf bit of the sspxstat regis- ter or the sspov bit of the sspxcon1 register are set when a byte is received. when the module is addressed, after the eighth falling edge of sclx on the bus, the acktim bit of the sspxcon3 register is set. the acktim bit indicates the acknowledge time of the active bus. the acktim status bit is only active when the ahen bit or dhen bit is enabled. 21.5 i 2 c slave mode operation the mssp slave mode operates in one of four modes selected in the sspm bits of sspxcon1 register. the modes can be divided into 7-bit and 10-bit addressing mode. 10-bit addressing modes operate the same as 7-bit with some additional overhead for handling the larger addresses. modes with start and stop bit interrupts operate the same as the other modes with sspxif additionally getting set upon detection of a start, restart, or stop condition. 21.5.1 slave mode addresses the sspxadd register ( register 21-6 ) contains the slave mode address. the first byte received after a start or restart condition is compared against the value stored in this register. if the byte matches, the value is loaded into the sspxbuf register and an interrupt is generated. if the value does not match, the module goes idle and no indication is given to the soft- ware that anything happened. the ssp mask register ( register 21-5 ) affects the address matching process. see section 21.5.9 ?sspx mask register? for more information. 21.5.1.1 i 2 c slave 7-bit addressing mode in 7-bit addressing mode, the lsb of the received data byte is ignored when determining if there is an address match. 21.5.1.2 i 2 c slave 10-bit addressing mode in 10-bit addressing mode, the first received byte is compared to the binary value of ?1 1 1 1 0 a9 a8 0?. a9 and a8 are the two msbs of the 10-bit address and stored in bits 2 and 1 of the sspxadd register. after the acknowledge of the high byte the ua bit is set and sclx is held low until the user updates sspxadd with the low address. the low address byte is clocked in and all eight bits are compared to the low address value in sspxadd. even if there is not an address match; sspxif and ua are set, and sclx is held low until sspxadd is updated to receive a high byte again. when sspxadd is updated the ua bit is cleared. this ensures the module is ready to receive the high address byte on the next communication. a high and low address match as a write request is required at the start of all 10-bit addressing communi- cation. a transmission can be initiated by issuing a restart once the slave is addressed, and clocking in the high address with the r/w bit set. the slave hard- ware will then acknowledge the read request and pre- pare to clock out data. this is only valid for a slave after it has received a complete high and low address byte match. 21.5.2 slave reception when the r/w bit of a matching received address byte is clear, the r/w bit of the sspxstat register is cleared. the received address is loaded into the sspxbuf register and acknowledged. when the overflow condition exists for a received address, then not acknowledge is given. an overflow condition is defined as either bit bf of the sspxstat register is set, or bit sspov of the sspxcon1 register is set. the boen bit of the sspxcon3 register modi- fies this operation. for more information see register 21-4 . an mssp interrupt is generated for each transferred data byte. flag bit, sspxif, must be cleared by soft- ware. when the sen bit of the sspxcon2 register is set, sclx will be held low (clock stretch) following each received byte. the clock must be released by setting the ckp bit of the sspxcon1 register, except sometimes in 10-bit mode. see section 21.2.3 ?spi master mode? for more detail.
pic16(l)f1508/9 ds40001609b-page 196 ? 2011-2013 microchip technology inc. 21.5.2.1 7-bit addressing reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 7-bit addressing mode. figure 21-14 and figure 21-15 are used as visual references for this description. this is a step by step process of what typically must be done to accomplish i 2 c communication. 1. start bit detected. 2. s bit of sspxstat is set; sspxif is set if inter- rupt on start detect is enabled. 3. matching address with r/w bit clear is received. 4. the slave pulls sdax low sending an ack to the master, and sets sspxif bit. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. if sen = 1 ; slave software sets ckp bit to release the sclx line. 8. the master clocks out a data byte. 9. slave drives sdax low sending an ack to the master, and sets sspxif bit. 10. software clears sspxif. 11. software reads the received byte from sspxbuf clearing bf. 12. steps 8-12 are repeated for all received bytes from the master. 13. master sends stop condition, setting p bit of sspxstat, and the bus goes idle. 21.5.2.2 7-bit reception with ahen and dhen slave device reception with ahen and dhen set operate the same as without these options with extra interrupts and clock stretching added after the eighth falling edge of sclx. these additional interrupts allow the slave software to decide whether it wants to ack the receive address or data byte, rather than the hard- ware. this functionality adds support for pmbus? that was not present on previous versions of this module. this list describes the steps that need to be taken by slave software to use these options for i 2 c communi- cation. figure 21-16 displays a module using both address and data holding. figure 21-17 includes the operation with the sen bit of the sspxcon2 register set. 1. s bit of sspxstat is set; sspxif is set if inter- rupt on start detect is enabled. 2. matching address with r/w bit clear is clocked in. sspxif is set and ckp cleared after the eighth falling edge of sclx. 3. slave clears the sspxif. 4. slave can look at the acktim bit of the sspxcon3 register to determine if the sspxif was after or before the ack. 5. slave reads the address value from sspxbuf, clearing the bf flag. 6. slave sets ack value clocked out to the master by setting ackdt. 7. slave releases the clock by setting ckp. 8. sspxif is set after an ack , not after a nack. 9. if sen = 1 the slave hardware will stretch the clock after the ack. 10. slave clears sspxif. 11. sspxif set and ckp cleared after eighth falling edge of sclx for a received data byte. 12. slave looks at acktim bit of sspxcon3 to determine the source of the interrupt. 13. slave reads the received data from sspxbuf clearing bf. 14. steps 7-14 are the same for each received data byte. 15. communication is ended by either the slave sending an ack = 1 , or the master sending a stop condition. if a stop is sent and interrupt on stop detect is disabled, the slave will only know by polling the p bit of the sspstat register. note: sspxif is still set after the ninth falling edge of sclx even if there is no clock stretching and bf has been cleared. only if nack is sent to master is sspxif not set
? 2011-2013 microchip technology inc. ds40001609b-page 197 pic16(l)f1508/9 figure 21-14: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving data ack receiving data ack = 1 a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf sspov 12345678 12345678 12345678 9 9 9 ack is not sent. sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf sspxbuf is read sspxif set on 9th falling edge of sclx cleared by software p bus master sends stop condition s from slave to master
pic16(l)f1508/9 ds40001609b-page 198 ? 2011-2013 microchip technology inc. figure 21-15: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sen sen a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx 123456789 123456789 123456789 p sspxif set on 9th sclx is not held ckp is written to ? 1 ? in software, ckp is written to ? 1 ? in software, ack low because falling edge of sclx releasing sclx ack is not sent. bus master sends ckp sspov bf sspxif sspov set because sspxbuf is still full. cleared by software first byte of data is available in sspxbuf ack = 1 cleared by software sspxbuf is read clock is held low until ckp is set to ? 1 ? releasing sclx stop condition s ack ack receive address receive data receive data r/w= 0
? 2011-2013 microchip technology inc. ds40001609b-page 199 pic16(l)f1508/9 figure 21-16: i 2 c slave, 7-bit address, reception (sen = 0 , ahen = 1 , dhen = 1 ) receiving address receiving data received data p a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx bf ckp s p 12 3 4 56 7 8 9 12345678 9 12345678 master sends stop condition s data is read from sspxbuf cleared by software sspxif is set on 9th falling edge of sclx, after ack ckp set by software, sclx is released slave software 9 acktim cleared by hardware in 9th rising edge of sclx sets ackdt to not ack when dhen= 1 : ckp is cleared by hardware on 8th falling edge of sclx slave software clears ackdt to ack the received byte acktim set by hardware on 8th falling edge of sclx when ahen= 1 : ckp is cleared by hardware and sclx is stretched address is read from ssbuf acktim set by hardware on 8th falling edge of sclx ack master releases sdax to slave for ack sequence no interrupt after not ack from slave ack = 1 ack ackdt acktim sspxif if ahen = 1 : sspxif is set
pic16(l)f1508/9 ds40001609b-page 200 ? 2011-2013 microchip technology inc. figure 21-17: i 2 c slave, 7-bit address, reception (sen = 1 , ahen = 1 , dhen = 1 ) receiving address receive data receive data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf ackdt ckp s p ack s 12 34 5678 9 12 3 4567 8 9 12 345 67 8 9 ack ack cleared by software acktim is cleared by hardware sspxbuf can be set by software, read any time before next byte is loaded release sclx on 9th rising edge of sclx received address is loaded into sspxbuf slave software clears ackdt to ack r/w = 0 master releases sdax to slave for ack sequence the received byte when ahen = 1 ; on the 8th falling edge of sclx of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of sclx when dhen = 1 ; on the 8th falling edge of sclx of a received data byte, ckp is cleared received data is available on sspxbuf slave sends not ack ckp is not cleared if not ack p master sends stop condition no interrupt after if not ack from slave acktim
? 2011-2013 microchip technology inc. ds40001609b-page 201 pic16(l)f1508/9 21.5.3 slave transmission when the r/w bit of the incoming address byte is set and an address match occurs, the r/w bit of the sspxstat register is set. the received address is loaded into the sspxbuf register, and an ack pulse is sent by the slave on the ninth bit. following the ack , slave hardware clears the ckp bit and the sclx pin is held low (see section 21.5.6 ?clock stretching? for more detail). by stretching the clock, the master will be unable to assert another clock pulse until the slave is done preparing the transmit data. the transmit data must be loaded into the sspxbuf register which also loads the sspxsr register. then the sclx pin should be released by setting the ckp bit of the sspxcon1 register. the eight data bits are shifted out on the falling edge of the sclx input. this ensures that the sdax signal is valid during the sclx high time. the ack pulse from the master-receiver is latched on the rising edge of the ninth sclx input pulse. this ack value is copied to the ackstat bit of the sspxcon2 register. if ackstat is set (not ack ), then the data transfer is complete. in this case, when the not ack is latched by the slave, the slave goes idle and waits for another occurrence of the start bit. if the sdax line was low (ack ), the next transmit data must be loaded into the sspxbuf register. again, the sclx pin must be released by setting bit ckp. an mssp interrupt is generated for each data transfer byte. the sspxif bit must be cleared by software and the sspxstat register is used to determine the status of the byte. the sspxif bit is set on the falling edge of the ninth clock pulse. 21.5.3.1 slave mode bus collision a slave receives a read request and begins shifting data out on the sdax line. if a bus collision is detected and the sbcde bit of the sspxcon3 register is set, the bclxif bit of the pirx register is set. once a bus collision is detected, the slave goes idle and waits to be addressed again. user software can use the bclxif bit to handle a slave bus collision. 21.5.3.2 7-bit transmission a master device can transmit a read request to a slave, and then clock data out of the slave. the list below outlines what software for a slave will need to do to accomplish a standard transmission. figure 21-18 can be used as a reference to this list. 1. master sends a start condition on sdax and sclx. 2. s bit of sspxstat is set; sspxif is set if inter- rupt on start detect is enabled. 3. matching address with r/w bit set is received by the slave setting sspxif bit. 4. slave hardware generates an ack and sets sspxif. 5. sspxif bit is cleared by user. 6. software reads the received address from sspxbuf, clearing bf. 7. r/w is set so ckp was automatically cleared after the ack. 8. the slave software loads the transmit data into sspxbuf. 9. ckp bit is set releasing sclx, allowing the mas- ter to clock the data out of the slave. 10. sspxif is set after the ack response from the master is loaded into the ackstat register. 11. sspxif bit is cleared. 12. the slave software checks the ackstat bit to see if the master wants to clock out more data. 13. steps 9-13 are repeated for each transmitted byte. 14. if the master sends a not ack ; the clock is not held, but sspxif is still set. 15. the master sends a restart condition or a stop. 16. the slave is no longer addressed. note 1: if the master ack s the clock will be stretched. 2: ackstat is the only bit updated on the rising edge of sclx (ninth) rather than the falling.
pic16(l)f1508/9 ds40001609b-page 202 ? 2011-2013 microchip technology inc. figure 21-18: i 2 c slave, 7-bit address, transmission (ahen = 0 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sdax sclx sspxif bf ckp ackstat r/w d/a s p received address when r/w is set r/w is copied from the indicates an address is read from sspxbuf sclx is always held low after 9th sclx falling edge matching address byte has been received masters not ack is copied to ackstat ckp is not held for not ack bf is automatically cleared after 8th falling edge of sclx data to transmit is loaded into sspxbuf set by software cleared by software ack ack ack r/w = 1 s p master sends stop condition
? 2011-2013 microchip technology inc. ds40001609b-page 203 pic16(l)f1508/9 21.5.3.3 7-bit transmission with address hold enabled setting the ahen bit of the sspxcon3 register enables additional clock stretching and interrupt gen- eration after the eighth falling edge of a received matching address. once a matching address has been clocked in, ckp is cleared and the sspxif inter- rupt is set. figure 21-19 displays a standard waveform of a 7-bit address slave transmission with ahen enabled. 1. bus starts idle. 2. master sends start condition; the s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching address with r/w bit set. after the eighth falling edge of the sclx line the ckp bit is cleared and sspxif interrupt is generated. 4. slave software clears sspxif. 5. slave software reads acktim bit of sspxcon3 register, and r/w and d/a of the sspxstat register to determine the source of the interrupt. 6. slave reads the address value from the sspxbuf register clearing the bf bit. 7. slave software decides from this information if it wishes to ack or not ack and sets the ackdt bit of the sspxcon2 register accordingly. 8. slave sets the ckp bit releasing sclx. 9. master clocks in the ack value from the slave. 10. slave hardware automatically clears the ckp bit and sets sspxif after the ack if the r/w bit is set. 11. slave software clears sspxif. 12. slave loads value to transmit to the master into sspxbuf setting the bf bit. 13. slave sets the ckp bit, releasing the clock. 14. master clocks out the data from the slave and sends an ack value on the ninth sclx pulse. 15. slave hardware copies the ack value into the ackstat bit of the sspxcon2 register. 16. steps 10-15 are repeated for each byte trans- mitted to the master from the slave. 17. if the master sends a not ack the slave releases the bus allowing the master to send a stop and end the communication. note: sspxbuf cannot be loaded until after the ack. note: master must send a not ack on the last byte to ensure that the slave releases the sclx line to receive a stop.
pic16(l)f1508/9 ds40001609b-page 204 ? 2011-2013 microchip technology inc. figure 21-19: i 2 c slave, 7-bit address, transmission (ahen = 1 ) receiving address automatic transmitting data automatic transmitting data a7 a6 a5 a4 a3 a2 a1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 9 sdax sclx sspxif bf ackdt ackstat ckp r/w d/a received address is read from sspxbuf bf is automatically cleared after 8th falling edge of sclx data to transmit is loaded into sspxbuf cleared by software slave clears ackdt to ack address master?s ack response is copied to sspxstat ckp not cleared after not ack set by software, releases sclx acktim is cleared on 9th rising edge of sclx acktim is set on 8th falling edge of sclx when ahen = 1 ; ckp is cleared by hardware after receiving matching address. when r/w = 1 ; ckp is always cleared after ack s p master sends stop condition ack r/w = 1 master releases sdax to slave for ack sequence ack ack acktim
? 2011-2013 microchip technology inc. ds40001609b-page 205 pic16(l)f1508/9 21.5.4 slave mode 10-bit address reception this section describes a standard sequence of events for the mssp module configured as an i 2 c slave in 10-bit addressing mode. figure 21-20 is used as a visual reference for this description. this is a step by step process of what must be done by slave software to accomplish i 2 c communication. 1. bus starts idle. 2. master sends start condition; s bit of sspxstat is set; sspxif is set if interrupt on start detect is enabled. 3. master sends matching high address with r/w bit clear; ua bit of the sspxstat register is set. 4. slave sends ack and sspxif is set. 5. software clears the sspxif bit. 6. software reads received address from sspxbuf clearing the bf flag. 7. slave loads low address into sspxadd, releasing sclx. 8. master sends matching low address byte to the slave; ua bit is set. 9. slave sends ack and sspxif is set. 10. slave clears sspxif. 11. slave reads the received matching address from sspxbuf clearing bf. 12. slave loads high address into sspxadd. 13. master clocks a data byte to the slave and clocks out the slaves ack on the ninth sclx pulse; sspxif is set. 14. if sen bit of sspxcon2 is set, ckp is cleared by hardware and the clock is stretched. 15. slave clears sspxif. 16. slave reads the received byte from sspxbuf clearing bf. 17. if sen is set the slave sets ckp to release the sclx. 18. steps 13-17 repeat for each received byte. 19. master sends stop to end the transmission. 21.5.5 10-bit addressing with address or data hold reception using 10-bit addressing with ahen or dhen set is the same as with 7-bit modes. the only difference is the need to update the sspxadd register using the ua bit. all functionality, specifically when the ckp bit is cleared and sclx line is held low are the same. figure 21-21 can be used as a reference of a slave in 10-bit addressing with ahen set. figure 21-22 shows a standard waveform for a slave transmitter in 10-bit addressing mode. note: updates to the sspxadd register are not allowed until after the ack sequence. note: if the low address does not match, sspxif and ua are still set so that the slave soft- ware can set sspxadd back to the high address. bf is not set because there is no match. ckp is unaffected.
pic16(l)f1508/9 ds40001609b-page 206 ? 2011-2013 microchip technology inc. figure 21-20: i 2 c slave, 10-bit address, reception (sen = 1 , ahen = 0 , dhen = 0 ) sspxif receive first address byte ack receive second address byte ack receive data ack receive data ack 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx ua ckp 1 2345678 912345678 912345678 9 12345678 9 p master sends stop condition cleared by software receive address is software updates sspxadd data is read sclx is held low set by software, while ckp = 0 from sspxbuf releasing sclx when sen = 1 ; ckp is cleared after 9th falling edge of received byte read from sspxbuf and releases sclx when ua = 1 ; if address matches set by hardware on 9th falling edge sspxadd it is loaded into sspxbuf sclx is held low s bf
? 2011-2013 microchip technology inc. ds40001609b-page 207 pic16(l)f1508/9 figure 21-21: i 2 c slave, 10-bit address, reception (sen = 0 , ahen = 1 , dhen = 0 ) receive first address byte ua receive second address byte ua receive data ack receive data 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 sdax sclx sspxif bf ackdt ua ckp acktim 12345678 9 s ack ack 12 345678 9 12345678 91 2 sspxbuf is read from received data sspxbuf can be read anytime before the next received byte cleared by software falling edge of sclx not allowed until 9th update to sspxadd is set ckp with software releases sclx sclx clears ua and releases update of sspxadd, set by hardware on 9th falling edge slave software clears ackdt to ack the received byte if when ahen = 1 ; on the 8th falling edge of sclx of an address byte, ckp is cleared acktim is set by hardware on 8th falling edge of sclx cleared by software r/w = 0
pic16(l)f1508/9 ds40001609b-page 208 ? 2011-2013 microchip technology inc. figure 21-22: i 2 c slave, 10-bit address, transmission (sen = 0 , ahen = 0 , dhen = 0 ) receiving address ack receiving second address byte sr receive first address byte ack transmitting data byte 1 1 1 1 0 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 1 1 1 1 0 a9 a8 d7 d6 d5 d4 d3 d2 d1 d0 sdax sclx sspxif bf ua ckp r/w d/a 1 2345 6789 1 2345 6789 1 23 4 5 6789 1 23456 789 ack = 1 p master sends stop condition master sends not ack master sends restart event ack r/w = 0 s cleared by software after sspxadd is updated, ua is cleared and sclx is released high address is loaded received address is data to transmit is set by software indicates an address when r/w = 1 ; r/w is copied from the set by hardware ua indicates sspxadd sspxbuf loaded with received address must be updated has been received loaded into sspxbuf releases sclx masters not ack is copied matching address byte ckp is cleared on 9th falling edge of sclx read from sspxbuf back into sspxadd ackstat set by hardware
? 2011-2013 microchip technology inc. ds40001609b-page 209 pic16(l)f1508/9 21.5.6 clock stretching clock stretching occurs when a device on the bus holds the sclx line low, effectively pausing communi- cation. the slave may stretch the clock to allow more time to handle data or prepare a response for the mas- ter device. a master device is not concerned with stretching as anytime it is active on the bus and not transferring data it is stretching. any stretching done by a slave is invisible to the master software and han- dled by the hardware that generates sclx. the ckp bit of the sspxcon1 register is used to con- trol stretching in software. any time the ckp bit is cleared, the module will wait for the sclx line to go low and then hold it. setting ckp will release sclx and allow more communication. 21.5.6.1 normal clock stretching following an ack if the r/w bit of sspxstat is set, a read request, the slave hardware will clear ckp. this allows the slave time to update sspxbuf with data to transfer to the master. if the sen bit of sspxcon2 is set, the slave hardware will always stretch the clock after the ack sequence. once the slave is ready, ckp is set by software and communication resumes. 21.5.6.2 10-bit addressing mode in 10-bit addressing mode, when the ua bit is set, the clock is always stretched. this is the only time the sclx is stretched without ckp being cleared. sclx is released immediately after a write to sspxadd. 21.5.6.3 byte nacking when the ahen bit of sspxcon3 is set; ckp is cleared by hardware after the eighth falling edge of sclx for a received matching address byte. when the dhen bit of sspxcon3 is set, ckp is cleared after the eighth falling edge of sclx for received data. stretching after the eighth falling edge of sclx allows the slave to look at the received address or data and decide if it wants to ack the received data. 21.5.7 clock synchronization and the ckp bit any time the ckp bit is cleared, the module will wait for the sclx line to go low and then hold it. however, clearing the ckp bit will not assert the sclx output low until the sclx output is already sampled low. therefore, the ckp bit will not assert the sclx line until an external i 2 c master device has already asserted the sclx line. the sclx output will remain low until the ckp bit is set and all other devices on the i 2 c bus have released sclx. this ensures that a write to the ckp bit will not violate the minimum high time requirement for sclx (see figure 21-23 ). figure 21-23: clock synchronization timing note 1: the bf bit has no effect on if the clock will be stretched or not. this is different than previous versions of the module that would not stretch the clock, clear ckp, if sspxbuf was read before the ninth fall- ing edge of sclx. 2: previous versions of the module did not stretch the clock for a transmission if sspxbuf was loaded before the ninth falling edge of sclx. it is now always cleared for read requests. note: previous versions of the module did not stretch the clock if the second address byte did not match. sdax sclx dx ? ? 1 dx wr q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 sspxcon1 ckp master device releases clock master device asserts clock
pic16(l)f1508/9 ds40001609b-page 210 ? 2011-2013 microchip technology inc. 21.5.8 general call address support the addressing procedure for the i 2 c bus is such that the first byte after the start condition usually deter- mines which device will be the slave addressed by the master device. the exception is the general call address which can address all devices. when this address is used, all devices should, in theory, respond with an acknowledge. the general call address is a reserved address in the i 2 c protocol, defined as address 0x00. when the gcen bit of the sspxcon2 register is set, the slave module will automatically ack the reception of this address regardless of the value stored in sspxadd. after the slave clocks in an address of all zeros with the r/w bit clear, an interrupt is generated and slave software can read sspxbuf and respond. figure 21-24 shows a general call reception sequence. in 10-bit address mode, the ua bit will not be set on the reception of the general call address. the slave will prepare to receive the second byte as data, just as it would in 7-bit mode. if the ahen bit of the sspxcon3 register is set, just as with any other address reception, the slave hard- ware will stretch the clock after the eighth falling edge of sclx. the slave must then set its ackdt value and release the clock with communication progressing as it would normally. figure 21-24: slave mode general call address sequence 21.5.9 sspx mask register an sspx mask (sspxmsk) register ( register 21-5 ) is available in i 2 c slave mode as a mask for the value held in the sspxsr register during an address comparison operation. a zero (? 0 ?) bit in the sspxmsk register has the effect of making the corresponding bit of the received address a ?don?t care?. this register is reset to all ? 1 ?s upon any reset condition and, therefore, has no effect on standard sspx operation until written with a mask value. the sspx mask register is active during: ? 7-bit address mode: address compare of a<7:1>. ? 10-bit address mode: address compare of a<7:0> only. the sspx mask has no effect during the reception of the first (high) byte of the address. sdax sclx s sspxif bf (sspxstat<0>) cleared by software sspxbuf is read r/w = 0 ack general call address address is compared to general call address receiving data ack 123456789123456789 d7 d6 d5 d4 d3 d2 d1 d0 after ack , set interrupt gcen (sspxcon2<7>) ?1?
? 2011-2013 microchip technology inc. ds40001609b-page 211 pic16(l)f1508/9 21.6 i 2 c master mode master mode is enabled by setting and clearing the appropriate sspm bits in the sspxcon1 register and by setting the sspen bit. in master mode, the sdax and sckx pins must be configured as inputs. the mssp peripheral hardware will override the output driver tris controls when necessary to drive the pins low. master mode of operation is supported by interrupt generation on the detection of the start and stop con- ditions. the stop (p) and start (s) bits are cleared from a reset or when the msspx module is disabled. con- trol of the i 2 c bus may be taken when the p bit is set, or the bus is idle. in firmware controlled master mode, user code conducts all i 2 c bus operations based on start and stop bit condition detection. start and stop condition detection is the only active circuitry in this mode. all other communication is done by the user software directly manipulating the sdax and sclx lines. the following events will cause the sspx interrupt flag bit, sspxif, to be set (sspx interrupt, if enabled): ? start condition detected ? stop condition detected ? data transfer byte transmitted/received ? acknowledge transmitted/received ? repeated start generated 21.6.1 i 2 c master mode operation the master device generates all of the serial clock pulses and the start and stop conditions. a transfer is ended with a stop condition or with a repeated start condition. since the repeated start condition is also the beginning of the next serial transfer, the i 2 c bus will not be released. in master transmitter mode, serial data is output through sdax, while sclx outputs the serial clock. the first byte transmitted contains the slave address of the receiving device (seven bits) and the read/write (r/w ) bit. in this case, the r/w bit will be logic ? 0 ?. serial data is transmitted eight bits at a time. after each byte is transmitted, an acknowledge bit is received. start and stop conditions are output to indicate the beginning and the end of a serial transfer. in master receive mode, the first byte transmitted contains the slave address of the transmitting device (seven bits) and the r/w bit. in this case, the r/w bit will be logic ? 1 ?. thus, the first byte transmitted is a 7-bit slave address followed by a ? 1 ? to indicate the receive bit. serial data is received via sdax, while sclx out- puts the serial clock. serial data is received eight bits at a time. after each byte is received, an acknowledge bit is transmitted. start and stop conditions indicate the beginning and end of transmission. a baud rate generator is used to set the clock frequency output on sclx. see section 21.7 ?baud rate generator? for more detail. note 1: the msspx module, when configured in i 2 c master mode, does not allow queue- ing of events. for instance, the user is not allowed to initiate a start condition and immediately write the sspxbuf register to initiate transmission before the start condition is complete. in this case, the sspxbuf will not be written to and the wcol bit will be set, indicating that a write to the sspxbuf did not occur 2: when in master mode, start/stop detec- tion is masked and an interrupt is gener- ated when the sen/pen bit is cleared and the generation is complete.
pic16(l)f1508/9 ds40001609b-page 212 ? 2011-2013 microchip technology inc. 21.6.2 clock arbitration clock arbitration occurs when the master, during any receive, transmit or repeated start/stop condition, releases the sclx pin (sclx allowed to float high). when the sclx pin is allowed to float high, the baud rate generator (brg) is suspended from counting until the sclx pin is actually sampled high. when the sclx pin is sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and begins counting. this ensures that the sclx high time will always be at least one brg rollover count in the event that the clock is held low by an external device ( figure 21-25 ). figure 21-25: baud rate generator timing with clock arbitration 21.6.3 wcol status flag if the user writes the sspxbuf when a start, restart, stop, receive or transmit sequence is in progress, the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). any time the wcol bit is set it indicates that an action on sspxbuf was attempted while the module was not idle. sdax sclx sclx deasserted but slave holds dx ? ? 1 dx brg sclx is sampled high, reload takes place and brg starts its count 03h 02h 01h 00h (hold off) 03h 02h reload brg value sclx low (clock arbitration) sclx allowed to transition high brg decrements on q2 and q4 cycles note: because queueing of events is not allowed, writing to the lower five bits of sspxcon2 is disabled until the start condition is complete.
? 2011-2013 microchip technology inc. ds40001609b-page 213 pic16(l)f1508/9 21.6.4 i 2 c master mode start condition timing to initiate a start condition ( figure 21-26 ), the user sets the start enable bit, sen bit of the sspxcon2 register. if the sdax and sclx pins are sampled high, the baud rate generator is reloaded with the contents of sspxadd<7:0> and starts its count. if sclx and sdax are both sampled high when the baud rate generator times out (t brg ), the sdax pin is driven low. the action of the sdax being driven low while sclx is high is the start condition and causes the s bit of the sspxstat1 register to be set. following this, the baud rate generator is reloaded with the contents of sspxadd<7:0> and resumes its count. when the baud rate generator times out (t brg ), the sen bit of the sspxcon2 register will be automatically cleared by hardware; the baud rate generator is suspended, leaving the sdax line held low and the start condition is complete. figure 21-26: first start bit timing note 1: if at the beginning of the start condition, the sdax and sclx pins are already sam- pled low, or if during the start condition, the sclx line is sampled low before the sdax line is driven low, a bus collision occurs, the bus collision interrupt flag, bclxif, is set, the start condition is aborted and the i 2 c module is reset into its idle state. 2: the philips i 2 c specification states that a bus collision cannot occur on a start. sdax sclx s t brg 1st bit 2nd bit t brg sdax = 1 , at completion of start bit, sclx = 1 write to sspxbuf occurs here t brg hardware clears sen bit t brg write to sen bit occurs here set s bit (sspxstat<3>) and sets sspxif bit
pic16(l)f1508/9 ds40001609b-page 214 ? 2011-2013 microchip technology inc. 21.6.5 i 2 c master mode repeated start condition timing a repeated start condition ( figure 21-27 ) occurs when the rsen bit of the sspxcon2 register is pro- grammed high and the master state machine is no lon- ger active. when the rsen bit is set, the sclx pin is asserted low. when the sclx pin is sampled low, the baud rate generator is loaded and begins counting. the sdax pin is released (brought high) for one baud rate generator count (t brg ). when the baud rate generator times out, if sdax is sampled high, the sclx pin will be deasserted (brought high). when sclx is sampled high, the baud rate generator is reloaded and begins counting. sdax and sclx must be sam- pled high for one t brg . this action is then followed by assertion of the sdax pin (sdax = 0 ) for one t brg while sclx is high. sclx is asserted low. following this, the rsen bit of the sspxcon2 register will be automatically cleared and the baud rate generator will not be reloaded, leaving the sdax pin held low. as soon as a start condition is detected on the sdax and sclx pins, the s bit of the sspxstat register will be set. the sspxif bit will not be set until the baud rate generator has timed out. figure 21-27: repeat start condition waveform note 1: if rsen is programmed while any other event is in progress, it will not take effect. 2: a bus collision during the repeated start condition occurs if: ? sdax is sampled low when sclx goes from low-to-high. ? sclx goes low before sdax is asserted low. this may indicate that another master is attempting to transmit a data ? 1 ?. sdax sclx repeated start write to sspxcon2 write to sspxbuf occurs here at completion of start bit, hardware clears rsen bit 1st bit s bit set by hardware t brg t brg sdax = 1 , sdax = 1 , sclx (no change) sclx = 1 occurs here t brg t brg t brg and sets sspxif sr
? 2011-2013 microchip technology inc. ds40001609b-page 215 pic16(l)f1508/9 21.6.6 i 2 c master mode transmission transmission of a data byte, a 7-bit address or the other half of a 10-bit address is accomplished by simply writing a value to the sspxbuf register. this action will set the buffer full flag bit, bf, and allow the baud rate generator to begin counting and start the next trans- mission. each bit of address/data will be shifted out onto the sdax pin after the falling edge of sclx is asserted. sclx is held low for one baud rate genera- tor rollover count (t brg ). data should be valid before sclx is released high. when the sclx pin is released high, it is held that way for t brg . the data on the sdax pin must remain stable for that duration and some hold time after the next falling edge of sclx. after the eighth bit is shifted out (the falling edge of the eighth clock), the bf flag is cleared and the master releases sdax. this allows the slave device being addressed to respond with an ack bit during the ninth bit time if an address match occurred, or if data was received prop- erly. the status of ack is written into the ackstat bit on the rising edge of the ninth clock. if the master receives an acknowledge, the acknowledge status bit, ackstat, is cleared. if not, the bit is set. after the ninth clock, the sspxif bit is set and the master clock (baud rate generator) is suspended until the next data byte is loaded into the sspxbuf, leaving sclx low and sdax unchanged ( figure 21-28 ). after the write to the sspxbuf, each bit of the address will be shifted out on the falling edge of sclx until all seven address bits and the r/w bit are completed. on the falling edge of the eighth clock, the master will release the sdax pin, allowing the slave to respond with an acknowledge. on the falling edge of the ninth clock, the master will sample the sdax pin to see if the address was recognized by a slave. the status of the ack bit is loaded into the ackstat status bit of the sspxcon2 register. following the falling edge of the ninth clock transmission of the address, the sspxif is set, the bf flag is cleared and the baud rate generator is turned off until another write to the sspxbuf takes place, holding sclx low and allowing sdax to float. 21.6.6.1 bf status flag in transmit mode, the bf bit of the sspxstat register is set when the cpu writes to sspxbuf and is cleared when all eight bits are shifted out. 21.6.6.2 wcol status flag if the user writes the sspxbuf when a transmit is already in progress (i.e., sspxsr is still shifting out a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). wcol must be cleared by software before the next transmission. 21.6.6.3 ackstat status flag in transmit mode, the ackstat bit of the sspxcon2 register is cleared when the slave has sent an acknowl- edge (ack = 0 ) and is set when the slave does not acknowledge (ack = 1 ). a slave sends an acknowl- edge when it has recognized its address (including a general call), or when the slave has properly received its data. 21.6.6.4 typical transmit sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. the msspx module will wait the required start time before any other operation takes place. 5. the user loads the sspxbuf with the slave address to transmit. 6. address is shifted out the sdax pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 7. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 8. the msspx module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 9. the user loads the sspxbuf with eight bits of data. 10. data is shifted out the sdax pin until all eight bits are transmitted. 11. the msspx module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 12. steps 8-11 are repeated for all transmitted data bytes. 13. the user generates a stop or restart condition by setting the pen or rsen bits of the sspxcon2 register. interrupt is generated once the stop/restart condition is complete.
pic16(l)f1508/9 ds40001609b-page 216 ? 2011-2013 microchip technology inc. figure 21-28: i 2 c master mode waveform (transmission, 7 or 10-bit address) sdax sclx sspxif bf (sspxstat<0>) sen a7 a6 a5 a4 a3 a2 a1 ack = 0 d7 d6 d5 d4 d3 d2 d1 d0 ack transmitting data or second half r/w = 0 transmit address to slave 123456789 123456789 p cleared by software service routine sspxbuf is written by software from ssp interrupt after start condition, sen cleared by hardware s sspxbuf written with 7-bit address and r/w start transmit sclx held low while cpu responds to sspxif sen = 0 of 10-bit address write sspxcon2<0> sen = 1 start condition begins from slave, clear ackstat bit sspxcon2<6> ackstat in sspxcon2 = 1 cleared by software sspxbuf written pen r/w cleared by software
? 2011-2013 microchip technology inc. ds40001609b-page 217 pic16(l)f1508/9 21.6.7 i 2 c master mode reception master mode reception ( figure 21-29 ) is enabled by programming the receive enable bit, rcen bit of the sspxcon2 register. the baud rate generator begins counting and on each rollover, the state of the sclx pin changes (high-to-low/low-to-high) and data is shifted into the sspxsr. after the falling edge of the eighth clock, the receive enable flag is automatically cleared, the con- tents of the sspxsr are loaded into the sspxbuf, the bf flag bit is set, the sspxif flag bit is set and the baud rate generator is suspended from counting, holding sclx low. the mssp is now in idle state awaiting the next command. when the buffer is read by the cpu, the bf flag bit is automatically cleared. the user can then send an acknowledge bit at the end of reception by setting the acknowledge sequence enable, acken bit of the sspxcon2 register. 21.6.7.1 bf status flag in receive operation, the bf bit is set when an address or data byte is loaded into sspxbuf from sspxsr. it is cleared when the sspxbuf register is read. 21.6.7.2 sspov status flag in receive operation, the sspov bit is set when eight bits are received into the sspxsr and the bf flag bit is already set from a previous reception. 21.6.7.3 wcol status flag if the user writes the sspxbuf when a receive is already in progress (i.e., sspxsr is still shifting in a data byte), the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 21.6.7.4 typical receive sequence: 1. the user generates a start condition by setting the sen bit of the sspxcon2 register. 2. sspxif is set by hardware on completion of the start. 3. sspxif is cleared by software. 4. user writes sspxbuf with the slave address to transmit and the r/w bit set. 5. address is shifted out the sdax pin until all eight bits are transmitted. transmission begins as soon as sspxbuf is written to. 6. the mssp module shifts in the ack bit from the slave device and writes its value into the ackstat bit of the sspxcon2 register. 7. the mssp module generates an interrupt at the end of the ninth clock cycle by setting the sspxif bit. 8. user sets the rcen bit of the sspxcon2 regis- ter and the master clocks in a byte from the slave. 9. after the eighth falling edge of sclx, sspxif and bf are set. 10. master clears sspxif and reads the received byte from sspxbuf, clears bf. 11. master sets ack value sent to slave in ackdt bit of the sspxcon2 register and initiates the ack by setting the acken bit. 12. masters ack is clocked out to the slave and sspxif is set. 13. user clears sspxif. 14. steps 8-13 are repeated for each received byte from the slave. 15. master sends a not ack or stop to end communication. note: the msspx module must be in an idle state before the rcen bit is set or the rcen bit will be disregarded.
pic16(l)f1508/9 ds40001609b-page 218 ? 2011-2013 microchip technology inc. figure 21-29: i 2 c master mode waveform (reception, 7-bit address) p 9 8 7 6 5 d0 d1 d2 d3 d4 d5 d6 d7 s a7 a6 a5 a4 a3 a2 a1 sdax sclx 12 3 4 5 6 7 8 9 12 3 4 5 678 9 1234 bus master terminates transfer ack receiving data from slave receiving data from slave d0 d1 d2 d3 d4 d5 d6 d7 ack r/w transmit address to slave sspxif bf ack is not sent write to sspxcon2<0>(sen = 1 ), write to sspxbuf occurs here, ack from slave master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) pen bit = 1 written here data shifted in on falling edge of clk cleared by software start xmit sen = 0 sspov sdax = 0 , sclx = 1 while cpu (sspxstat<0>) ack cleared by software cleared by software set sspxif interrupt at end of receive set p bit (sspxstat<4>) and sspxif cleared in software ack from master set sspxif at end set sspxif interrupt at end of acknowledge sequence set sspxif interrupt at end of acknow- ledge sequence of receive set acken, start acknowledge sequence sspov is set because sspxbuf is still full sdax = ackdt = 1 rcen cleared automatically rcen = 1 , start next receive write to sspxcon2<4> to start acknowledge sequence sdax = ackdt (sspxcon2<5>) = 0 rcen cleared automatically responds to sspxif acken begin start condition cleared by software sdax = ackdt = 0 last bit is shifted into sspxsr and contents are unloaded into sspxbuf rcen master configured as a receiver by programming sspxcon2<3> (rcen = 1 ) rcen cleared automatically ack from master sdax = ackdt = 0 rcen cleared automatically
? 2011-2013 microchip technology inc. ds40001609b-page 219 pic16(l)f1508/9 21.6.8 acknowledge sequence timing an acknowledge sequence is enabled by setting the acknowledge sequence enable bit, acken bit of the sspxcon2 register. when this bit is set, the sclx pin is pulled low and the contents of the acknowledge data bit are presented on the sdax pin. if the user wishes to generate an acknowledge, then the ackdt bit should be cleared. if not, the user should set the ackdt bit before starting an acknowledge sequence. the baud rate generator then counts for one rollover period (t brg ) and the sclx pin is deasserted (pulled high). when the sclx pin is sampled high (clock arbitration), the baud rate generator counts for t brg . the sclx pin is then pulled low. following this, the acken bit is auto- matically cleared, the baud rate generator is turned off and the mssp module then goes into idle mode ( figure 21-30 ). 21.6.8.1 wcol status flag if the user writes the sspxbuf when an acknowledge sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). 21.6.9 stop condition timing a stop bit is asserted on the sdax pin at the end of a receive/transmit by setting the stop sequence enable bit, pen bit of the sspxcon2 register. at the end of a receive/transmit, the sclx line is held low after the falling edge of the ninth clock. when the pen bit is set, the master will assert the sdax line low. when the sdax line is sampled low, the baud rate generator is reloaded and counts down to ? 0 ?. when the baud rate generator times out, the sclx pin will be brought high and one t brg (baud rate generator rollover count) later, the sdax pin will be deasserted. when the sdax pin is sampled high while sclx is high, the p bit of the sspxstat register is set. a t brg later, the pen bit is cleared and the sspxif bit is set ( figure 21-31 ). 21.6.9.1 wcol status flag if the user writes the sspxbuf when a stop sequence is in progress, then the wcol bit is set and the contents of the buffer are unchanged (the write does not occur). figure 21-30: acknowledge sequen ce waveform note: t brg = one baud rate generator period. sdax sclx sspxif set at acknowledge sequence starts here, write to sspxcon2 acken automatically cleared cleared in t brg t brg the end of receive 8 acken = 1 , ackdt = 0 d0 9 sspxif software sspxif set at the end of acknowledge sequence cleared in software ack
pic16(l)f1508/9 ds40001609b-page 220 ? 2011-2013 microchip technology inc. figure 21-31: stop cond ition receive or transmit mode 21.6.10 sleep operation while in sleep mode, the i 2 c slave module can receive addresses or data and when an address match or complete byte transfer occurs, wake the processor from sleep (if the mssp interrupt is enabled). 21.6.11 effects of a reset a reset disables the mssp module and terminates the current transfer. 21.6.12 multi-master mode in multi-master mode, the interrupt generation on the detection of the start and stop conditions allows the determination of when the bus is free. the stop (p) and start (s) bits are cleared from a reset or when the mssp module is disabled. control of the i 2 c bus may be taken when the p bit of the sspxstat register is set, or the bus is idle, with both the s and p bits clear. when the bus is busy, enabling the ssp interrupt will generate the interrupt when the stop condition occurs. in multi-master mode, the sdax line must be monitored for arbitration to see if the signal level is the expected output level. this check is performed by hardware with the result placed in the bclxif bit. the states where arbitration can be lost are: ? address transfer ? data transfer ? a start condition ? a repeated start condition ? an acknowledge condition 21.6.13 multi -master communication, bus collision and bus arbitration multi-master mode support is achieved by bus arbitra- tion. when the master outputs address/data bits onto the sdax pin, arbitration takes place when the master outputs a ? 1 ? on sdax, by letting sdax float high and another master asserts a ? 0 ?. when the sclx pin floats high, data should be stable. if the expected data on sdax is a ? 1 ? and the data sampled on the sdax pin is ? 0 ?, then a bus collision has taken place. the master will set the bus collision interrupt flag, bclxif and reset the i 2 c port to its idle state ( figure 21-32 ). if a transmit was in progress when the bus collision occurred, the transmission is halted, the bf flag is cleared, the sdax and sclx lines are deasserted and the sspxbuf can be written to. when the user ser- vices the bus collision interrupt service routine and if the i 2 c bus is free, the user can resume communica- tion by asserting a start condition. if a start, repeated start, stop or acknowledge condi- tion was in progress when the bus collision occurred, the condition is aborted, the sdax and sclx lines are deas- serted and the respective control bits in the sspxcon2 register are cleared. when the user services the bus col- lision interrupt service routine and if the i 2 c bus is free, the user can resume communication by asserting a start condition. the master will continue to monitor the sdax and sclx pins. if a stop condition occurs, the sspxif bit will be set. a write to the sspxbuf will start the transmission of data at the first data bit, regardless of where the transmitter left off when the bus collision occurred. in multi-master mode, the interrupt generation on the detection of start and stop conditions allows the deter- mination of when the bus is free. control of the i 2 c bus can be taken when the p bit is set in the sspxstat register, or the bus is idle and the s and p bits are cleared. sclx sdax sdax asserted low before rising edge of clock write to sspxcon2, set pen falling edge of sclx = 1 for t brg , followed by sdax = 1 for t brg 9th clock sclx brought high after t brg note: t brg = one baud rate generator period. t brg t brg after sdax sampled high. p bit (sspxstat<4>) is set. t brg to setup stop condition ack p t brg pen bit (sspxcon2<2 >) is cleared by hardware and the sspxif bit is set
? 2011-2013 microchip technology inc. ds40001609b-page 221 pic16(l)f1508/9 figure 21-32: bus collision timing for transmit and acknowledge sdax sclx bclxif sdax released sdax line pulled low by another source sample sdax. while sclx is high, data does not match what is driven bus collision has occurred. set bus collision interrupt (bclxif) by the master. by master data changes while sclx = 0
pic16(l)f1508/9 ds40001609b-page 222 ? 2011-2013 microchip technology inc. 21.6.13.1 bus collision during a start condition during a start condition, a bus collision occurs if: a) sda or scl are sampled low at the beginning of the start condition ( figure 21-33 ). b) scl is sampled low before sdax is asserted low ( figure 21-34 ). during a start condition, both the sdax and the scl pins are monitored. if the sda pin is already low, or the scl pin is already low, then all of the following occur: ? the start condition is aborted, ? the bcl1if flag is set and ? the mssp module is reset to its idle state ( figure 21-33 ). the start condition begins with the sdax and sclx pins deasserted. when the sdax pin is sampled high, the baud rate generator is loaded and counts down. if the sclx pin is sampled low while sdax is high, a bus collision occurs because it is assumed that another master is attempting to drive a data ? 1 ? during the start condition. if the sdax pin is sampled low during this count, the brg is reset and the sdax line is asserted early ( figure 21-35 ). if, however, a ? 1 ? is sampled on the sda pin, the sda pin is asserted low at the end of the brg count. the baud rate generator is then reloaded and counts down to zero; if the scl pin is sampled as ? 0 ? during this time, a bus collision does not occur. at the end of the brg count, the scl pin is asserted low. figure 21-33: bus collision during st art condition (sdax only) note: the reason that bus collision is not a fac- tor during a start condition is that no two bus masters can assert a start condition at the exact same time. therefore, one master will always assert sdax before the other. this condition does not cause a bus collision because the two masters must be allowed to arbitrate the first address fol- lowing the start condition. if the address is the same, arbitration must be allowed to continue into the data portion, repeated start or stop conditions. sdax sclx sen sdax sampled low before sdax goes low before the sen bit is set. s bit and sspxif set because ssp module reset into idle state. sen cleared automatically because of bus collision. s bit and sspxif set because set sen, enable start condition if sdax = 1 , sclx = 1 sdax = 0 , sclx = 1 . bclxif s sspxif sdax = 0 , sclx = 1 . sspxif and bclxif are cleared by software sspxif and bclxif are cleared by software set bclxif, start condition. set bclxif.
? 2011-2013 microchip technology inc. ds40001609b-page 223 pic16(l)f1508/9 figure 21-34: bus collision d uring start condition (sclx = 0 ) figure 21-35: brg reset due to sda arbitration during start condition sdax sclx sen bus collision occurs. set bclxif. sclx = 0 before sdax = 0 , set sen, enable start sequence if sdax = 1 , sclx = 1 t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif interrupt cleared by software bus collision occurs. set bclxif. sclx = 0 before brg time-out, ? 0 ?? 0 ? ? 0 ? ? 0 ? sdax sclx sen set s less than t brg t brg sdax = 0 , sclx = 1 bclxif s sspxif s interrupts cleared by software set sspxif sdax = 0 , sclx = 1 , sclx pulled low after brg time-out set sspxif ? 0 ? sdax pulled low by other master. reset brg and assert sdax. set sen, enable start sequence if sdax = 1 , sclx = 1
pic16(l)f1508/9 ds40001609b-page 224 ? 2011-2013 microchip technology inc. 21.6.13.2 bus collision during a repeated start condition during a repeated start condition, a bus collision occurs if: a) a low level is sampled on sdax when sclx goes from low level to high level (case 1). b) sclx goes low before sdax is asserted low, indicating that another master is attempting to transmit a data ? 1 ? (case 2). when the user releases sdax and the pin is allowed to float high, the brg is loaded with sspxadd and counts down to zero. the sclx pin is then deasserted and when sampled high, the sdax pin is sampled. if sdax is low, a bus collision has occurred (i.e., another master is attempting to transmit a data ? 0 ?, figure 21-36 ). if sdax is sampled high, the brg is reloaded and begins counting. if sdax goes from high-to-low before the brg times out, no bus collision occurs because no two masters can assert sdax at exactly the same time. if sclx goes from high-to-low before the brg times out and sdax has not already been asserted, a bus collision occurs. in this case, another master is attempting to transmit a data ? 1 ? during the repeated start condition, see figure 21-37 . if, at the end of the brg time-out, both sclx and sdax are still high, the sdax pin is driven low and the brg is reloaded and begins counting. at the end of the count, regardless of the status of the sclx pin, the sclx pin is driven low and the repeated start condition is complete. figure 21-36: bus collision during a repeat ed start condition (case 1) figure 21-37: bus collision during repeat ed start condition (case 2) sdax sclx rsen bclxif s sspxif sample sdax when sclx goes high. if sdax = 0 , set bclxif and release sdax and sclx. cleared by software ? 0 ? ? 0 ? sdax sclx bclxif rsen s sspxif interrupt cleared by software sclx goes low before sdax, set bclxif. release sdax and sclx. t brg t brg ? 0 ?
? 2011-2013 microchip technology inc. ds40001609b-page 225 pic16(l)f1508/9 21.6.13.3 bus collision during a stop condition bus collision occurs during a stop condition if: a) after the sdax pin has been deasserted and allowed to float high, sdax is sampled low after the brg has timed out (case 1). b) after the sclx pin is deasserted, sclx is sampled low before sdax goes high (case 2). the stop condition begins with sdax asserted low. when sdax is sampled low, the sclx pin is allowed to float. when the pin is sampled high (clock arbitration), the baud rate generator is loaded with sspxadd and counts down to 0. after the brg times out, sdax is sampled. if sdax is sampled low, a bus collision has occurred. this is due to another master attempting to drive a data ? 0 ? ( figure 21-38 ). if the sclx pin is sampled low before sdax is allowed to float high, a bus collision occurs. this is another case of another master attempting to drive a data ? 0 ? ( figure 21-39 ). figure 21-38: bus collision during a stop condition (case 1) figure 21-39: bus collision during a stop condition (case 2) sdax sclx bclxif pen p sspxif t brg t brg t brg sdax asserted low sdax sampled low after t brg , set bclxif ? 0 ? ? 0 ? sdax sclx bclxif pen p sspxif t brg t brg t brg assert sdax sclx goes low before sdax goes high, set bclxif ? 0 ? ? 0 ?
pic16(l)f1508/9 ds40001609b-page 226 ? 2011-2013 microchip technology inc. table 21-3: summary of registers associated with i 2 c? operation name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reset values on page: intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 ssp1add add<7:0> 233 ssp1buf mssp receive buffer/transmit register 183 * ssp1con1 wcol sspov sspen ckp sspm<3:0> 230 ssp1con2 gcen ackstat ackdt acken rcen pen rsen sen 231 ssp1con3 acktim pcie scie boen sdaht sbcde ahen dhen 232 ssp1msk msk<7:0> 233 ssp1stat smp cke d/a psr/w ua bf 228 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used by the mssp module in i 2 c? mode. * page provides register information. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 227 pic16(l)f1508/9 21.7 baud rate generator the mssp module has a baud rate generator avail- able for clock generation in both i 2 c and spi master modes. the baud rate generator (brg) reload value is placed in the sspxadd register ( register 21-6 ). when a write occurs to sspxbuf, the baud rate gen- erator will automatically begin counting down. once the given operation is complete, the internal clock will automatically stop counting and the clock pin will remain in its last state. an internal signal ?reload? in figure 21-40 triggers the value from sspxadd to be loaded into the brg counter. this occurs twice for each oscillation of the module clock line. the logic dictating when the reload signal is asserted depends on the mode the mssp is being operated in. table 21-4 demonstrates clock rates based on instruction cycles and the brg value loaded into sspxadd. equation 21-1: figure 21-40: baud rate genera tor block diagram table 21-4: mssp clock rate w/brg f clock f osc sspxadd 1 + ?? 4 ?? ------------------------------------------------- = note: values of 0x00, 0x01 and 0x02 are not valid for sspxadd when used as a baud rate generator for i 2 c. this is an implementation limitation. f osc f cy brg value f clock (two rollovers of brg) 16 mhz 4 mhz 09h 400 khz 16 mhz 4 mhz 0ch 308 khz 16 mhz 4 mhz 27h 100 khz 4 mhz 1 mhz 09h 100 khz note: refer to the i/o port electrical specifications in table 29-4 to ensure the system is designed to support lol requirements. sspm<3:0> brg down counter sspxclk f osc /2 sspxadd<7:0> sspm<3:0> sclx reload control reload
pic16(l)f1508/9 ds40001609b-page 228 ? 2011-2013 microchip technology inc. 21.8 register definitions: mssp control register 21-1: sspxstat: ssp status register r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 r-0/0 smp cke d/a psr/w ua bf bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = val ue at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 smp: spi data input sample bit spi master mode: 1 = input data sampled at end of data output time 0 = input data sampled at middle of data output time spi slave mode: smp must be cleared when spi is used in slave mode in i 2 c master or slave mode: 1 = slew rate control disabled 0 = slew rate control enabled bit 6 cke: spi clock edge select bit (spi mode only) in spi master or slave mode: 1 = transmit occurs on transition from active to idle clock state 0 = transmit occurs on transition from idle to active clock state in i 2 c ? mode only: 1 = enable input logic so that thresholds are compliant with smbus specification 0 = disable smbus specific inputs bit 5 d/a : data/address bit (i 2 c mode only) 1 = indicates that the last byte received or transmitted was data 0 = indicates that the last byte received or transmitted was address bit 4 p: stop bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a stop bit has been detected last (this bit is ? 0 ? on reset) 0 = stop bit was not detected last bit 3 s: start bit (i 2 c mode only. this bit is cleared when the ms sp module is disabled, sspen is cleared.) 1 = indicates that a start bit has been detected last (this bit is ? 0 ? on reset) 0 = start bit was not detected last bit 2 r/w : read/write bit information (i 2 c mode only) this bit holds the r/w bit information following the last address match. this bit is only valid from the address match to the next start bit, stop bit, or not ack bit. in i 2 c slave mode: 1 = read 0 = write in i 2 c master mode: 1 = transmit is in progress 0 = transmit is not in progress or-ing this bit with sen, rsen, pen, rcen or acken will indicate if the mssp is in idle mode. bit 1 ua: update address bit (10-bit i 2 c mode only) 1 = indicates that the user needs to update the address in the sspxadd register 0 = address does not need to be updated
? 2011-2013 microchip technology inc. ds40001609b-page 229 pic16(l)f1508/9 bit 0 bf: buffer full status bit receive (spi and i 2 c modes): 1 = receive complete, sspxbuf is full 0 = receive not complete, sspxbuf is empty transmit (i 2 c mode only): 1 = data transmit in progress (does not include the ack and stop bits), sspxbuf is full 0 = data transmit complete (does not include the ack and stop bits), sspxbuf is empty register 21-1: sspxstat: ssp status register (continued)
pic16(l)f1508/9 ds40001609b-page 230 ? 2011-2013 microchip technology inc. register 21-2: sspxcon1: ssp control register 1 r/c/hs-0/0 r/c/hs-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 wcol sspov (1) sspen ckp sspm<3:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hs = bit is set by hardware c = user cleared bit 7 wcol: write collision detect bit master mode: 1 = a write to the sspxbuf register was attempted while the i 2 c conditions were not valid for a transmission to be started 0 = no collision slave mode: 1 = the sspxbuf register is written while it is still transmitting the previous word (must be cleared in software) 0 = no collision bit 6 sspov: receive overflow indicator bit (1) in spi mode: 1 = a new byte is received while the sspxbuf register is still hold ing the previous data. in case of overflow, the data in sspxsr is lost. overflow can only occur in slave mode. in slave mode, the user must read the sspxbuf, even if only transmitting data, to avoid setting overflow. in master mode, the overfl ow bit is not set since each new recepti on (and transmission) is initiated by writi ng to the sspxbuf register (must be cleared in software). 0 = no overflow in i 2 c mode: 1 = a byte is received while the sspxbuf register is still holding the previous byte. sspov is a ?don?t care? in transmit mode (must be cleared in software). 0 = no overflow bit 5 sspen: synchronous serial port enable bit in both modes, when enabled, these pins must be properly configured as input or output in spi mode: 1 = enables serial port and configures sckx, sdox, sdix and ssx as the source of the serial port pins (2) 0 = disables serial port and configures these pins as i/o port pins in i 2 c mode: 1 = enables the serial port and configur es the sdax and sclx pins as t he source of the serial port pins (3) 0 = disables serial port and configures these pins as i/o port pins bit 4 ckp: clock polarity select bit in spi mode: 1 = idle state for clock is a high level 0 = idle state for clock is a low level in i 2 c slave mode: sclx release control 1 = enable clock 0 = holds clock low (clo ck stretch). (used to ensure data setup time.) in i 2 c master mode: unused in this mode bit 3-0 sspm<3:0>: synchronous serial port mode select bits 0000 = spi master mode, clock = f osc /4 0001 = spi master mode, clock = f osc /16 0010 = spi master mode, clock = f osc /64 0011 = spi master mode, clock = t2_match/2 0100 = spi slave mode, clock = sckx pin, ss pin control enabled 0101 = spi slave mode, clock = sckx pin, ss pin control disabled, ssx can be used as i/o pin 0110 = i 2 c slave mode, 7-bit address 0111 = i 2 c slave mode, 10-bit address 1000 = i 2 c master mode, clock = f osc /(4 * (sspxadd+1)) (4) 1001 = reserved 1010 = spi master mode, clock = f osc /(4 * (sspxadd+1)) (5) 1011 = i 2 c firmware controlled master mode (slave idle) 1100 = reserved 1101 = reserved 1110 = i 2 c slave mode, 7-bit address with start and stop bit interrupts enabled 1111 = i 2 c slave mode, 10-bit address with star t and stop bit interrupts enabled note 1: in master mode, the overflow bit is not se t since each new reception (and transmission) is initiated by writing to the sspxbuf register. 2: when enabled, these pins must be properly configured as input or output. 3: when enabled, the sdax and sclx pins must be configured as inputs. 4: sspxadd values of 0, 1 or 2 are not supported for i 2 c mode. 5: sspxadd value of ? 0 ? is not supported. use sspm = 0000 instead.
? 2011-2013 microchip technology inc. ds40001609b-page 231 pic16(l)f1508/9 register 21-3: sspxcon2: ssp control register 2 (1) r/w-0/0 r-0/0 r/w-0/0 r/s/hs-0/0 r/s/hs- 0/0 r/s/hs-0/0 r/s/hs-0/0 r/w/hs-0/0 gcen ackstat ackdt acken rcen pen rsen sen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared hc = cleared by hardware s = user set bit 7 gcen: general call enable bit (in i 2 c slave mode only) 1 = enable interrupt when a general call address (0x00 or 00h) is received in the sspxsr 0 = general call address disabled bit 6 ackstat: acknowledge status bit (in i 2 c mode only) 1 = acknowledge was not received 0 = acknowledge was received bit 5 ackdt: acknowledge data bit (in i 2 c mode only) in receive mode: value transmitted when the user initiates an acknowledge sequence at the end of a receive 1 = not acknowledge 0 = acknowledge bit 4 acken: acknowledge sequence enable bit (in i 2 c master mode only) in master receive mode: 1 = initiate acknowledge sequence on sdax and sclx pins, and transmit ackdt data bit. automatically cleared by hardware. 0 = acknowledge sequence idle bit 3 rcen: receive enable bit (in i 2 c master mode only) 1 = enables receive mode for i 2 c 0 = receive idle bit 2 pen: stop condition enable bit (in i 2 c master mode only) sckx release control: 1 = initiate stop condition on sdax and sclx pins. automatically cleared by hardware. 0 = stop condition idle bit 1 rsen: repeated start condition enable bit (in i 2 c master mode only) 1 = initiate repeated start condition on sdax and sclx pins. automatically cleared by hardware. 0 = repeated start condition idle bit 0 sen: start condition enable/stretch enable bit i n master mode: 1 = initiate start condition on sdax and sclx pins. automatically cleared by hardware. 0 = start condition idle in slave mode: 1 = clock stretching is enabled for both slave transmit and slave receive (stretch enabled) 0 = clock stretching is disabled note 1: for bits acken, rcen, pen, rsen, sen: if the i 2 c module is not in the idle mode, this bit may not be set (no spooling) and the sspxbuf may not be written (or writes to the sspxbuf are disabled).
pic16(l)f1508/9 ds40001609b-page 232 ? 2011-2013 microchip technology inc. register 21-4: sspxcon3: ssp control register 3 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 acktim (3) pcie scie boen sdaht sbcde ahen dhen bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 acktim: acknowledge time status bit (i 2 c mode only) (3) 1 = indicates the i 2 c bus is in an acknowledge sequence, set on eighth falling edge of sclx clock 0 = not an acknowledge sequence, cleared on ninth rising edge of sclx clock bit 6 pcie : stop condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of stop condition 0 = stop detection interrupts are disabled (2) bit 5 scie : start condition interrupt enable bit (i 2 c mode only) 1 = enable interrupt on detection of start or restart conditions 0 = start detection interrupts are disabled (2) bit 4 boen: buffer overwrite enable bit in spi slave mode: (1) 1 = sspxbuf updates every time that a new data byte is shifted in ignoring the bf bit 0 = if new byte is received with bf bit of the sspxstat register already set, sspov bit of the sspxcon1 register is set, and the buffer is not updated in i 2 c master mode: this bit is ignored. in i 2 c slave mode: 1 = sspxbuf is updated and ack is generated for a received address/data byte, ignoring the state of the sspov bit only if the bf bit = 0 . 0 = sspxbuf is only updated when sspov is clear bit 3 sdaht: sdax hold time selection bit (i 2 c mode only) 1 = minimum of 300 ns hold time on sdax after the falling edge of sclx 0 = minimum of 100 ns hold time on sdax after the falling edge of sclx bit 2 sbcde: slave mode bus collision detect enable bit (i 2 c slave mode only) if on the rising edge of sclx, sdax is sampled low when the module is outputting a high state, the bclxif bit of the pir2 register is set, and bus goes idle 1 = enable slave bus collision interrupts 0 = slave bus collision interrupts are disabled bit 1 ahen: address hold enable bit (i 2 c slave mode only) 1 = following the eighth falling edge of sclx for a matching received address byte, ckp bit of the sspxcon1 register will be cleared and the sclx will be held low. 0 = address holding is disabled bit 0 dhen: data hold enable bit (i 2 c slave mode only) 1 = following the eighth falling edge of sclx for a received data byte, slave hardware clears the ckp bit of the sspxcon1 register and sclx is held low. 0 = data holding is disabled note 1: for daisy-chained spi operation, allows the user to i gnore all but the last received byte. sspov is still set when a new byte is received and bf = 1 , but hardware continues to write the most recent byte to sspxbuf. 2: this bit has no effect in slave modes that start and stop condition detection is explicitly listed as enabled. 3: the acktim status bit is only active when the ahen bit or dhen bit is set.
? 2011-2013 microchip technology inc. ds40001609b-page 233 pic16(l)f1508/9 register 21-5: sspxmsk: ssp mask register r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 r/w-1/1 msk<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-1 msk<7:1>: mask bits 1 = the received address bit n is compared to sspxadd to detect i 2 c address match 0 = the received address bit n is not used to detect i 2 c address match bit 0 msk<0>: mask bit for i 2 c slave mode, 10-bit address i 2 c slave mode, 10-bit address (sspm<3:0> = 0111 or 1111 ): 1 = the received address bit 0 is compared to sspxadd<0> to detect i 2 c address match 0 = the received address bit 0 is not used to detect i 2 c address match i 2 c slave mode, 7-bit address, the bit is ignored register 21-6: sspxadd: mssp address and baud rate register (i 2 c mode) r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 add<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared master mode: bit 7-0 add<7:0>: baud rate clock divider bits sclx pin clock period = ((add<7:0> + 1) *4)/f osc 10-bit slave mode ? most significant address byte: bit 7-3 not used: unused for most significant address byte. bit state of this register is a ?don?t care?. bit pat- tern sent by master is fixed by i 2 c specification and must be equal to ? 11110 ?. however, those bits are compared by hardware and are not affected by the value in this register. bit 2-1 add<2:1>: two most significant bits of 10-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?. 10-bit slave mode ? least significant address byte: bit 7-0 add<7:0>: eight least significant bits of 10-bit address 7-bit slave mode: bit 7-1 add<7:1>: 7-bit address bit 0 not used: unused in this mode. bit state is a ?don?t care?.
pic16(l)f1508/9 ds40001609b-page 234 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 235 pic16(l)f1508/9 22.0 enhanced universal synchronous asynchronous receiver transmitter (eusart) the enhanced universal synchronous asynchronous receiver transmitter (eusart) module is a serial i/o communications peripheral. it contains all the clock generators, shift registers and data buffers necessary to perform an input or output serial data transfer independent of device program execution. the eusart, also known as a serial communications interface (sci), can be configured as a full-duplex asynchronous system or half-duplex synchronous system. full-duplex mode is useful for communications with peripheral systems, such as crt terminals and personal computers. half-duplex synchronous mode is intended for communications with peripheral devices, such as a/d or d/a integrated circuits, serial eeproms or other microcontrollers. these devices typically do not have internal clocks for baud rate generation and require the external clock signal provided by a master synchronous device. the eusart module includes the following capabilities: ? full-duplex asynchronous transmit and receive ? two-character input buffer ? one-character output buffer ? programmable 8-bit or 9-bit character length ? address detection in 9-bit mode ? input buffer overrun error detection ? received character framing error detection ? half-duplex synchronous master ? half-duplex synchronous slave ? programmable clock polarity in synchronous modes ? sleep operation the eusart module implements the following additional features, making it ideally suited for use in local interconnect network (lin) bus systems: ? automatic detection and calibration of the baud rate ? wake-up on break reception ? 13-bit break character transmit block diagrams of the eusart transmitter and receiver are shown in figure 22-1 and figure 22-2 . the eusart transmit output (tx_out) is available to the tx/ck pin and internally to the following peripherals: ? configurable logic cell (clc) figure 22-1: eusart transmi t block diagram txif txie interrupt txen tx9d msb lsb data bus txreg register transmit shift register (tsr) (8) 0 tx9 trmt tx/ck pin pin buffer and control 8 spbrgl spbrgh brg16 f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator ??? tx_out
pic16(l)f1508/9 ds40001609b-page 236 ? 2011-2013 microchip technology inc. figure 22-2: eusart receiv e block diagram the operation of the eusart module is controlled through three registers: ? transmit status and control (txsta) ? receive status and control (rcsta) ? baud rate control (baudcon) these registers are detailed in register 22-1 , register 22-2 and register 22-3 , respectively. when the receiver or transmitter section is not enabled then the corresponding rx or tx pin may be used for general purpose input and output. rx/dt pin pin buffer and control spen data recovery cren oerr ferr rsr register msb lsb rx9d rcreg register fifo interrupt rcif rcie data bus 8 stop start (8) 7 1 0 rx9 ? ? ? spbrgl spbrgh brg16 rcidl f osc n n + 1 multiplier x4 x16 x64 sync 1x00 0 brgh x110 0 brg16 x101 0 baud rate generator
? 2011-2013 microchip technology inc. ds40001609b-page 237 pic16(l)f1508/9 22.1 eusart asynchronous mode the eusart transmits and receives data using the standard non-return-to-zero (nrz) format. nrz is implemented with two levels: a v oh mark state which represents a ? 1 ? data bit, and a v ol space state which represents a ? 0 ? data bit. nrz refers to the fact that consecutively transmitted data bits of the same value stay at the output level of that bit without returning to a neutral level between each bit transmission. an nrz transmission port idles in the mark state. each character transmission consists of one start bit followed by eight or nine data bits and is always terminated by one or more stop bits. the start bit is always a space and the stop bits are always marks. the most common data format is eight bits. each transmitted bit persists for a period of 1/(baud rate). an on-chip dedicated 8-bit/16-bit baud rate generator is used to derive standard baud rate frequencies from the system oscillator. see tab l e 2 2- 5 for examples of baud rate configurations. the eusart transmits and receives the lsb first. the eusart?s transmitter and receiver are functionally independent, but share the same data format and baud rate. parity is not supported by the hardware, but can be implemented in software and stored as the ninth data bit. 22.1.1 eusart asynchronous transmitter the eusart transmitter block diagram is shown in figure 22-1 . the heart of the transmitter is the serial transmit shift register (tsr), which is not directly accessible by software. the tsr obtains its data from the transmit buffer, which is the txreg register. 22.1.1.1 enabling the transmitter the eusart transmitter is enabled for asynchronous operations by configuring the following three control bits: ?txen = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the txen bit of the txsta register enables the transmitter circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart and automatically configures the tx/ck i/o pin as an output. if the tx/ck pin is shared with an analog peripheral, the analog i/o function must be disabled by clearing the corresponding ansel bit. 22.1.1.2 transmitting data a transmission is initiated by writing a character to the txreg register. if this is the first character, or the previous character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr register. if the tsr still contains all or part of a previous character, the new character data is held in the txreg until the stop bit of the previous character has been transmitted. the pending character in the txreg is then transferred to the tsr in one t cy immediately following the stop bit transmission. the transmission of the start bit, data bits and stop bit sequence commences immediately following the transfer of the data to the tsr from the txreg. 22.1.1.3 transmit data polarity the polarity of the transmit data can be controlled with the sckp bit of the baudcon register. the default state of this bit is ? 0 ? which selects high true transmit idle and data bits. setting the sckp bit to ? 1 ? will invert the transmit data resulting in low true idle and data bits. the sckp bit controls transmit data polarity in asynchronous mode only. in synchronous mode, the sckp bit has a different function. see section 22.5.1.2 ?clock polarity? . 22.1.1.4 transmit interrupt flag the txif interrupt flag bit of the pir1 register is set whenever the eusart transmitter is enabled and no character is being held for transmission in the txreg. in other words, the txif bit is only clear when the tsr is busy with a character and a new character has been queued for transmission in the txreg. the txif flag bit is not cleared immediately upon writing txreg. txif becomes valid in the second instruction cycle following the write execution. polling txif immediately following the txreg write will return invalid results. the txif bit is read-only, it cannot be set or cleared by software. the txif interrupt can be enabled by setting the txie interrupt enable bit of the pie1 register. however, the txif flag bit will be set whenever the txreg is empty, regardless of the state of txie enable bit. to use interrupts when transmitting data, set the txie bit only when there is more data to send. clear the txie interrupt enable bit upon writing the last character of the transmission to the txreg. note: the txif transmitter interrupt flag is set when the txen enable bit is set.
pic16(l)f1508/9 ds40001609b-page 238 ? 2011-2013 microchip technology inc. 22.1.1.5 tsr status the trmt bit of the txsta register indicates the status of the tsr register. this is a read-only bit. the trmt bit is set when the tsr register is empty and is cleared when a character is transferred to the tsr register from the txreg. the trmt bit remains clear until all bits have been shifted out of the tsr register. no interrupt logic is tied to this bit, so the user has to poll this bit to determine the tsr status. 22.1.1.6 transmitting 9-bit characters the eusart supports 9-bit character transmissions. when the tx9 bit of the txsta register is set, the eusart will shift nine bits out for each character trans- mitted. the tx9d bit of the txsta register is the ninth, and most significant, data bit. when transmitting 9-bit data, the tx9d data bit must be written before writing the eight least significant bits into the txreg. all nine bits of data will be transferred to the tsr shift register immediately after the txreg is written. a special 9-bit address mode is available for use with multiple receivers. see section 22.1.2.7 ?address detection? for more information on the address mode. 22.1.1.7 asynchronous transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. enable the asynchronous serial port by clearing the sync bit and setting the spen bit. 3. if 9-bit transmission is desired, set the tx9 con- trol bit. a set ninth data bit will indicate that the eight least significant data bits are an address when the receiver is set for address detection. 4. set sckp bit if inverted transmit is desired. 5. enable the transmission by setting the txen control bit. this will cause the txif interrupt bit to be set. 6. if interrupts are desired, set the txie interrupt enable bit of the pie1 register. an interrupt will occur immediately provided that the gie and peie bits of the intcon register are also set. 7. if 9-bit transmission is selected, the ninth bit should be loaded into the tx9d data bit. 8. load 8-bit data into the txreg register. this will start the transmission. figure 22-3: asynchronous transmission figure 22-4: asynchronous transmiss ion (back-to-back) note: the tsr register is not mapped in data memory, so it is not available to the user. word 1 stop bit word 1 transmit shift reg. start bit bit 0 bit 1 bit 7/8 write to txreg word 1 brg output (shift clock) tx/ck txif bit (transmit buffer reg. empty flag) trmt bit (transmit shift reg. empty flag) 1 t cy pin transmit shift reg. write to txreg brg output (shift clock) tx/ck trmt bit (transmit shift reg. empty flag) word 1 word 2 word 1 word 2 start bit stop bit start bit transmit shift reg. word 1 word 2 bit 0 bit 1 bit 7/8 bit 0 note: this timing diagram shows two consecutive transmissions. 1 t cy 1 t cy pin txif bit (transmit buffer reg. empty flag)
? 2011-2013 microchip technology inc. ds40001609b-page 239 pic16(l)f1508/9 table 22-1: summary of registers asso ciated with asynchronous transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcsta spen rx9 sren cren adden ferr oerr rx9d 246 * spbrgl brg<7:0> 248 * spbrgh brg<15:8> 248 * trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txreg eusart transmit data register 237 txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for asynchronous transmission. * page provides register information.
pic16(l)f1508/9 ds40001609b-page 240 ? 2011-2013 microchip technology inc. 22.1.2 eusart asynchronous receiver the asynchronous mode is typically used in rs-232 systems. the receiver block diagram is shown in figure 22-2 . the data is received on the rx/dt pin and drives the data recovery block. the data recovery block is actually a high-speed shifter operating at 16 times the baud rate, whereas the serial receive shift register (rsr) operates at the bit rate. when all eight or nine bits of the character have been shifted in, they are immediately transferred to a two character first-in-first-out (fifo) memory. the fifo buffering allows reception of two complete characters and the start of a third character before software must start servicing the eusart receiver. the fifo and rsr registers are not directly accessible by software. access to the received data is via the rcreg register. 22.1.2.1 enabling the receiver the eusart receiver is enabled for asynchronous operation by configuring the following three control bits: ? cren = 1 ? sync = 0 ? spen = 1 all other eusart control bits are assumed to be in their default state. setting the cren bit of the rcsta register enables the receiver circuitry of the eusart. clearing the sync bit of the txsta register configures the eusart for asynchronous operation. setting the spen bit of the rcsta register enables the eusart. the programmer must set the corresponding tris bit to configure the rx/dt i/o pin as an input. 22.1.2.2 receiving data the receiver data recovery circuit initiates character reception on the falling edge of the first bit. the first bit, also known as the start bit, is always a zero. the data recovery circuit counts one-half bit time to the center of the start bit and verifies that the bit is still a zero. if it is not a zero then the data recovery circuit aborts character reception, without generating an error, and resumes looking for the falling edge of the start bit. if the start bit zero verification succeeds then the data recovery circuit counts a full bit time to the center of the next bit. the bit is then sampled by a majority detect circuit and the resulting ? 0 ? or ? 1 ? is shifted into the rsr. this repeats until all data bits have been sampled and shifted into the rsr. one final bit time is measured and the level sampled. this is the stop bit, which is always a ? 1 ?. if the data recovery circuit samples a ? 0 ? in the stop bit position then a framing error is set for this character, otherwise the framing error is cleared for this character. see section 22.1.2.4 ?receive framing error? for more information on framing errors. immediately after all data bits and the stop bit have been received, the character in the rsr is transferred to the eusart receive fifo and the rcif interrupt flag bit of the pir1 register is set. the top character in the fifo is transferred out of the fifo by reading the rcreg register. 22.1.2.3 receive interrupts the rcif interrupt flag bit of the pir1 register is set whenever the eusart receiver is enabled and there is an unread character in the receive fifo. the rcif interrupt flag bit is read-only, it cannot be set or cleared by software. rcif interrupts are enabled by setting all of the following bits: ? rcie, interrupt enable bit of the pie1 register ? peie, peripheral interrupt enable bit of the intcon register ? gie, global interrupt enable bit of the intcon register the rcif interrupt flag bit will be set when there is an unread character in the fifo, regardless of the state of interrupt enable bits. note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the receive fifo is overrun, no additional characters will be received until the overrun condition is cleared. see section 22.1.2.5 ?receive overrun error? for more information on overrun errors.
? 2011-2013 microchip technology inc. ds40001609b-page 241 pic16(l)f1508/9 22.1.2.4 receive framing error each character in the receive fifo buffer has a corresponding framing error status bit. a framing error indicates that a stop bit was not seen at the expected time. the framing error status is accessed via the ferr bit of the rcsta register. the ferr bit represents the status of the top unread character in the receive fifo. therefore, the ferr bit must be read before reading the rcreg. the ferr bit is read-only and only applies to the top unread character in the receive fifo. a framing error (ferr = 1 ) does not preclude reception of additional characters. it is not necessary to clear the ferr bit. reading the next character from the fifo buffer will advance the fifo to the next character and the next corresponding framing error. the ferr bit can be forced clear by clearing the spen bit of the rcsta register which resets the eusart. clearing the cren bit of the rcsta register does not affect the ferr bit. a framing error by itself does not generate an interrupt. 22.1.2.5 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before the fifo is accessed. when this happens the oerr bit of the rcsta register is set. the characters already in the fifo buffer can be read but no additional characters will be received until the error is cleared. the error must be cleared by either clearing the cren bit of the rcsta register or by resetting the eusart by clearing the spen bit of the rcsta register. 22.1.2.6 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift nine bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth and most significant data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcreg. 22.1.2.7 address detection a special address detection mode is available for use when multiple receivers share the same transmission line, such as in rs-485 systems. address detection is enabled by setting the adden bit of the rcsta register. address detection requires 9-bit character reception. when address detection is enabled, only characters with the ninth data bit set will be transferred to the receive fifo buffer, thereby setting the rcif interrupt bit. all other characters will be ignored. upon receiving an address character, user software determines if the address matches its own. upon address match, user software must disable address detection by clearing the adden bit before the next stop bit occurs. when user software detects the end of the message, determined by the message protocol used, software places the receiver back into the address detection mode by setting the adden bit. note: if all receive characters in the receive fifo have framing errors, repeated reads of the rcreg will not clear the ferr bit.
pic16(l)f1508/9 ds40001609b-page 242 ? 2011-2013 microchip technology inc. 22.1.2.8 asynchronous reception set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit reception is desired, set the rx9 bit. 6. enable reception by setting the cren bit. 7. the rcif interrupt flag bit will be set when a character is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 8. read the rcsta register to get the error flags and, if 9-bit data reception is enabled, the ninth data bit. 9. get the received eight least significant data bits from the receive buffer by reading the rcreg register. 10. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 22.1.2.9 9-bit address detection mode set-up this mode would typically be used in rs-485 systems. to set up an asynchronous reception with address detect enable: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. clear the ansel bit for the rx pin (if applicable). 3. enable the serial port by setting the spen bit. the sync bit must be clear for asynchronous operation. 4. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 5. enable 9-bit reception by setting the rx9 bit. 6. enable address detection by setting the adden bit. 7. enable reception by setting the cren bit. 8. the rcif interrupt flag bit will be set when a character with the ninth bit set is transferred from the rsr to the receive buffer. an interrupt will be generated if the rcie interrupt enable bit was also set. 9. read the rcsta register to get the error flags. the ninth data bit will always be set. 10. get the received eight least significant data bits from the receive buffer by reading the rcreg register. software determines if this is the device?s address. 11. if an overrun occurred, clear the oerr flag by clearing the cren receiver enable bit. 12. if the device has been addressed, clear the adden bit to allow all received data into the receive buffer and generate interrupts. figure 22-5: asynchronous reception start bit bit 7/8 bit 1 bit 0 bit 7/8 bit 0 stop bit start bit start bit bit 7/8 stop bit rx/dt pin reg rcv buffer reg. rcv shift read rcv buffer reg. rcreg rcif (interrupt flag) oerr bit cren word 1 rcreg word 2 rcreg stop bit note: this timing diagram shows three words appearing on the rx in put. the rcreg (receive buffer) is read after the third word, causing the oerr (overrun) bit to be set. rcidl
? 2011-2013 microchip technology inc. ds40001609b-page 243 pic16(l)f1508/9 table 22-2: summary of registers asso ciated with asynchronous reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ?wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcreg eusart receive data register 240 * rcsta spen rx9 sren cren adden ferr oerr rx9d 246 * spbrgl brg<7:0> 248 * spbrgh brg<15:8> 248 * trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for asynchronous reception. * page provides register information.
pic16(l)f1508/9 ds40001609b-page 244 ? 2011-2013 microchip technology inc. 22.2 clock accuracy with asynchronous operation the factory calibrates the internal oscillator block out- put (intosc). however, the intosc frequency may drift as v dd or temperature changes, and this directly affects the asynchronous baud rate. the auto-baud detect feature (see section 22.4.1 ?auto-baud detect? ) can be used to compensate for changes in the intosc frequency. there may not be fine enough resolution when adjusting the baud rate generator to compensate for a gradual change in the peripheral clock frequency.
? 2011-2013 microchip technology inc. ds40001609b-page 245 pic16(l)f1508/9 22.3 register definitions: eusart control register 22-1: txsta: transmit status and control register r/w-/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-1/1 r/w-0/0 csrc tx9 txen (1) sync sendb brgh trmt tx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 csrc: clock source select bit asynchronous mode : don?t care synchronous mode : 1 = master mode (clock generated internally from brg) 0 = slave mode (clock from external source) bit 6 tx9: 9-bit transmit enable bit 1 = selects 9-bit transmission 0 = selects 8-bit transmission bit 5 txen: transmit enable bit (1) 1 = transmit enabled 0 = transmit disabled bit 4 sync: eusart mode select bit 1 = synchronous mode 0 = asynchronous mode bit 3 sendb: send break character bit asynchronous mode : 1 = send sync break on next transmission (cleared by hardware upon completion) 0 = sync break transmission completed synchronous mode : don?t care bit 2 brgh: high baud rate select bit asynchronous mode : 1 = high speed 0 = low speed synchronous mode: unused in this mode bit 1 trmt: transmit shift register status bit 1 = tsr empty 0 = tsr full bit 0 tx9d: ninth bit of transmit data can be address/data bit or a parity bit. note 1: sren/cren overrides txen in sync mode.
pic16(l)f1508/9 ds40001609b-page 246 ? 2011-2013 microchip technology inc. register 22-2: rcsta: receive status and control register r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r-0/0 r-0/0 r-0/0 spen rx9 sren cren adden ferr oerr rx9d bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 spen: serial port enable bit 1 = serial port enabled (configures rx/dt and tx/ck pins as serial port pins) 0 = serial port disabled (held in reset) bit 6 rx9: 9-bit receive enable bit 1 = selects 9-bit reception 0 = selects 8-bit reception bit 5 sren: single receive enable bit asynchronous mode : don?t care synchronous mode ? master : 1 = enables single receive 0 = disables single receive this bit is cleared after reception is complete. synchronous mode ? slave don?t care bit 4 cren: continuous receive enable bit asynchronous mode : 1 = enables receiver 0 = disables receiver synchronous mode : 1 = enables continuous receive until enable bit cren is cleared (cren overrides sren) 0 = disables continuous receive bit 3 adden: address detect enable bit asynchronous mode 9-bit (rx9 = 1 ) : 1 = enables address detection, enable interrupt and load the receive buffer when rsr<8> is set 0 = disables address detection, all bytes are received and ninth bit can be used as parity bit asynchronous mode 8-bit (rx9 = 0 ) : don?t care bit 2 ferr: framing error bit 1 = framing error (can be updated by reading rcreg register and receive next valid byte) 0 = no framing error bit 1 oerr: overrun error bit 1 = overrun error (can be cleared by clearing bit cren) 0 = no overrun error bit 0 rx9d: ninth bit of received data this can be address/data bit or a parity bit and must be calculated by user firmware.
? 2011-2013 microchip technology inc. ds40001609b-page 247 pic16(l)f1508/9 register 22-3: baudcon: ba ud rate control register r-0/0 r-1/1 u-0 r/w-0/0 r/w-0/0 u-0 r/w-0/0 r/w-0/0 abdovf rcidl ? sckp brg16 ? wue abden bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 abdovf: auto-baud detect overflow bit asynchronous mode : 1 = auto-baud timer overflowed 0 = auto-baud timer did not overflow synchronous mode : don?t care bit 6 rcidl : receive idle flag bit asynchronous mode : 1 = receiver is idle 0 = start bit has been received and the receiver is receiving synchronous mode : don?t care bit 5 unimplemented: read as ? 0 ? bit 4 sckp : synchronous clock polarity select bit asynchronous mode : 1 = transmit inverted data to the tx/ck pin 0 = transmit non-inverted data to the tx/ck pin synchronous mode : 1 = data is clocked on rising edge of the clock 0 = data is clocked on falling edge of the clock bit 3 brg16: 16-bit baud rate generator bit 1 = 16-bit baud rate generator is used 0 = 8-bit baud rate generator is used bit 2 unimplemented: read as ? 0 ? bit 1 wue: wake-up enable bit asynchronous mode : 1 = receiver is waiting for a falling edge. no character will be received, rcif bit will be set. wue will automatically clear after rcif is set. 0 = receiver is operating normally synchronous mode : don?t care bit 0 abden : auto-baud detect enable bit asynchronous mode : 1 = auto-baud detect mode is enabled (clears when auto-baud is complete) 0 = auto-baud detect mode is disabled synchronous mode : don?t care
pic16(l)f1508/9 ds40001609b-page 248 ? 2011-2013 microchip technology inc. 22.4 eusart baud rate generator (brg) the baud rate generator (brg) is an 8-bit or 16-bit timer that is dedicated to the support of both the asynchronous and synchronous eusart operation. by default, the brg operates in 8-bit mode. setting the brg16 bit of the baudcon register selects 16-bit mode. the spbrgh, spbrgl register pair determines the period of the free running baud rate timer. in asynchronous mode the multiplier of the baud rate period is determined by both the brgh bit of the txsta register and the brg16 bit of the baudcon register. in synchronous mode, the brgh bit is ignored. table 22-3 contains the formulas for determining the baud rate. example 22-1 provides a sample calculation for determining the baud rate and baud rate error. typical baud rates and error values for various asynchronous modes have been computed for your convenience and are shown in table 22-3 . it may be advantageous to use the high baud rate (brgh = 1 ), or the 16-bit brg (brg16 = 1 ) to reduce the baud rate error. the 16-bit brg mode is used to achieve slow baud rates for fast oscillator frequencies. writing a new value to the spbrgh, spbrgl register pair causes the brg timer to be reset (or cleared). this ensures that the brg does not wait for a timer overflow before outputting the new baud rate. if the system clock is changed during an active receive operation, a receive error or data loss may result. to avoid this problem, check the status of the rcidl bit to make sure that the receive operation is idle before changing the system clock. example 22-1: calculating baud rate error for a device with f osc of 16 mhz, desired baud rate of 9600, asynchronous mode, 8-bit brg: solving for spbrgh:spbrgl: x f osc desired baud rate --------------------------------------------- 64 --------------------------------------------- 1 ? = desired baud rate f osc 64 [spbrgh:spbrgl] 1 + ?? ----------------------------------------------------------------------- - = 16000000 9600 ----------------------- - 64 ----------------------- -1 ? = 25.042 ?? 25 == calculated baud rate 16000000 64 25 1 + ?? -------------------------- - = 9615 = error calc. baud rate desired baud rate ? desired baud rate -------------------------------------------------------------------------------------------- = 9615 9600 ? ?? 9600 ---------------------------------- 0 . 1 6 % ==
? 2011-2013 microchip technology inc. ds40001609b-page 249 pic16(l)f1508/9 table 22-3: baud rate formulas table 22-4: summary of registers asso ciated with the baud rate generator configuration bits brg/eusart mode baud rate formula sync brg16 brgh 000 8-bit/asynchronous f osc /[64 (n+1)] 001 8-bit/asynchronous f osc /[16 (n+1)] 010 16-bit/asynchronous 011 16-bit/asynchronous f osc /[4 (n+1)] 10x 8-bit/synchronous 11x 16-bit/synchronous legend: x = don?t care, n = value of spbrgh, spbrgl register pair. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 247 rcsta spen rx9 sren cren adden ferr oerr rx9d 246 spbrgl brg<7:0> 248 * spbrgh brg<15:8> 248 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for the baud rate generator. * page provides register information.
pic16(l)f1508/9 ds40001609b-page 250 ? 2011-2013 microchip technology inc. table 22-5: baud rates for asynchronous modes baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300?? ? ?? ? ?? ? ?? ? 1200 1221 1.73 255 1200 0.00 239 1202 0.16 207 1200 0.00 143 2400 2404 0.16 129 2400 0.00 119 2404 0.16 103 2400 0.00 71 9600 9470 -1.36 32 9600 0.00 29 9615 0.16 25 9600 0.00 17 10417 10417 0.00 29 10286 -1.26 27 10417 0.00 23 10165 -2.42 16 19.2k 19.53k 1.73 15 19.20k 0.00 14 19.23k 0.16 12 19.20k 0.00 8 57.6k ? ? ? 57.60k 0.00 7? ? ? 57.60k 0.00 2 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ? ? ? 300 0.16 207 300 0.00 191 300 0.16 51 1200 1202 0.16 103 1202 0.16 51 1200 0.00 47 1202 0.16 12 2400 2404 0.16 51 2404 0.16 25 2400 0.00 23 ? ? ? 9600 9615 0.16 12 ? ? ? 9600 0.00 5 ? ? ? 10417 10417 0.00 11 10417 0.00 5 ? ? ? ? ? ? 19.2k ? ? ? ? ? ? 19.20k 0.00 2 ? ? ? 57.6k ? ? ? ? ? ? 57.60k 0.00 0 ? ? ? 115.2k ? ? ? ? ? ? ? ? ? ? ? ? baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ?? ? ?? ? ?? ? 1200 ? ? ? ? ? ? ? ? ? ? ? ? 2400 ? ? ? ? ? ? ? ? ? ?? ? 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.82k -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.64k -1.36 10 115.2k 0.00 9 111.1k -3.55 8 115.2k 0.00 5
? 2011-2013 microchip technology inc. ds40001609b-page 251 pic16(l)f1508/9 baud rate sync = 0 , brgh = 1 , brg16 = 0 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 ?? ? ? ? ? ? ? ? 300 0.16 207 1200 ? ? ? 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19231 0.16 25 19.23k 0.16 12 19.2k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 -0.01 4166 300.0 0.00 3839 300.03 0.01 3332 300.0 0.00 2303 1200 1200 -0.03 1041 1200 0.00 959 1200.5 0.04 832 1200 0.00 575 2400 2399 -0.03 520 2400 0.00 479 2398 -0.08 416 2400 0.00 287 9600 9615 0.16 129 9600 0.00 119 9615 0.16 103 9600 0.00 71 10417 10417 0.00 119 10378 -0.37 110 10417 0.00 95 10473 0.53 65 19.2k 19.23k 0.16 64 19.20k 0.00 59 19.23k 0.16 51 19.20k 0.00 35 57.6k 56.818 -1.36 21 57.60k 0.00 19 58.82k 2.12 16 57.60k 0.00 11 115.2k 113.636 -1.36 10 115.2k 0.00 9 111.11k -3.55 8 115.2k 0.00 5 baud rate sync = 0 , brgh = 0 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 299.9 -0.02 1666 300.1 0.04 832 300.0 0.00 767 300.5 0.16 207 1200 1199 -0.08 416 1202 0.16 207 1200 0.00 191 1202 0.16 51 2400 2404 0.16 207 2404 0.16 103 2400 0.00 95 2404 0.16 25 9600 9615 0.16 51 9615 0.16 25 9600 0.00 23 ? ? ? 10417 10417 0.00 47 10417 0.00 23 10473 0.53 21 10417 0.00 5 19.2k 19.23k 0.16 25 19.23k 0.16 12 19.20k 0.00 11 ? ? ? 57.6k 55556 -3.55 8 ? ? ? 57.60k 0.00 3 ? ? ? 115.2k ? ? ? ? ? ? 115.2k 0.00 1 ? ? ? table 22-5: baud rates for asynchronous modes (continued)
pic16(l)f1508/9 ds40001609b-page 252 ? 2011-2013 microchip technology inc. baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 20.000 mhz f osc = 18.432 mhz f osc = 16.000 mhz f osc = 11.0592 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 16665 300.0 0.00 15359 300.0 0.00 13332 300.0 0.00 9215 1200 1200 -0.01 4166 1200 0.00 3839 1200.1 0.01 3332 1200 0.00 2303 2400 2400 0.02 2082 2400 0.00 1919 2399.5 -0.02 1666 2400 0.00 1151 9600 9597 -0.03 520 9600 0.00 479 9592 -0.08 416 9600 0.00 287 10417 10417 0.00 479 10425 0.08 441 10417 0.00 383 10433 0.16 264 19.2k 19.23k 0.16 259 19.20k 0.00 239 19.23k 0.16 207 19.20k 0.00 143 57.6k 57.47k -0.22 86 57.60k 0.00 79 57.97k 0.64 68 57.60k 0.00 47 115.2k 116.3k 0.94 42 115.2k 0.00 39 114.29k -0.79 34 115.2k 0.00 23 baud rate sync = 0 , brgh = 1 , brg16 = 1 or sync = 1 , brg16 = 1 f osc = 8.000 mhz f osc = 4.000 mhz f osc = 3.6864 mhz f osc = 1.000 mhz actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) actual rate % error spbrg value (decimal) 300 300.0 0.00 6666 300.0 0.01 3332 300.0 0.00 3071 300.1 0.04 832 1200 1200 -0.02 1666 1200 0.04 832 1200 0.00 767 1202 0.16 207 2400 2401 0.04 832 2398 0.08 416 2400 0.00 383 2404 0.16 103 9600 9615 0.16 207 9615 0.16 103 9600 0.00 95 9615 0.16 25 10417 10417 0 191 10417 0.00 95 10473 0.53 87 10417 0.00 23 19.2k 19.23k 0.16 103 19.23k 0.16 51 19.20k 0.00 47 19.23k 0.16 12 57.6k 57.14k -0.79 34 58.82k 2.12 16 57.60k 0.00 15 ? ? ? 115.2k 117.6k 2.12 16 111.1k -3.55 8 115.2k 0.00 7 ? ? ? table 22-5: baud rates for asynchronous modes (continued)
? 2011-2013 microchip technology inc. ds40001609b-page 253 pic16(l)f1508/9 22.4.1 a uto-baud detect the eusart module supports automatic detection and calibration of the baud rate. in the auto-baud detect (abd) mode, the clock to the brg is reversed. rather than the brg clocking the incoming rx signal, the rx signal is timing the brg. the baud rate generator is used to time the period of a received 55h (ascii ?u?) which is the sync character for the lin bus. the unique feature of this character is that it has five rising edges including the stop bit edge. setting the abden bit of the baudcon register starts the auto-baud calibration sequence ( figure 22-6 ). while the abd sequence takes place, the eusart state machine is held in idle. on the first rising edge of the receive line, after the start bit, the spbrg begins counting up using the brg counter clock as shown in table 22-6 . the fifth rising edge will occur on the rx pin at the end of the eighth bit period. at that time, an accumulated value totaling the proper brg period is left in the spbrgh, spbrgl register pair, the abden bit is automatically cleared and the rcif interrupt flag is set. the value in the rcreg needs to be read to clear the rcif interrupt. rcreg content should be discarded. when calibrating for modes that do not use the spbrgh register the user can verify that the spbrgl register did not overflow by checking for 00h in the spbrgh register. the brg auto-baud clock is determined by the brg16 and brgh bits as shown in tab le 2 2- 6 . during abd, both the spbrgh and spbrgl registers are used as a 16-bit counter, independent of the brg16 bit setting. while calibrating the baud rate period, the spbrgh and spbrgl registers are clocked at 1/8th the brg base clock rate. the resulting byte measurement is the average bit time when clocked at full speed. table 22-6: brg counter clock rates figure 22-6: automatic baud rate calibration note 1: if the wue bit is set with the abden bit, auto-baud detection will occur on the byte following the break character (see section 22.4.3 ?auto-wake-up on break? ). 2: it is up to the user to determine that the incoming character baud rate is within the range of the selected brg clock source. some combinations of oscillator frequency and eusart baud rates are not possible. 3: during the auto-baud process, the auto-baud counter starts counting at 1. upon completion of the auto-baud sequence, to achieve maximum accuracy, subtract 1 from the spbrgh:spbrgl register pair. brg16 brgh brg base clock brg abd clock 00 f osc /64 f osc /512 01 f osc /16 f osc /128 10 f osc /16 f osc /128 11 f osc /4 f osc /32 note: during the abd sequence, spbrgl and spbrgh registers are both used as a 16-bit counter, independent of brg16 setting. brg value rx pin abden bit rcif bit bit 0 bit 1 (interrupt) read rcreg brg clock start auto cleared set by user xxxxh 0000h edge #1 bit 2 bit 3 edge #2 bit 4 bit 5 edge #3 bit 6 bit 7 edge #4 stop bit edge #5 001ch note 1: the abd sequence requires the eusart module to be configured in asynchronous mode. spbrgl xxh 1ch spbrgh xxh 00h rcidl
pic16(l)f1508/9 ds40001609b-page 254 ? 2011-2013 microchip technology inc. 22.4.2 auto-baud overflow during the course of automatic baud detection, the abdovf bit of the baudcon register will be set if the baud rate counter overflows before the fifth rising edge is detected on the rx pin. the abdovf bit indicates that the counter has exceeded the maximum count that can fit in the 16 bits of the spbrgh:spbrgl register pair. after the abdovf bit has been set, the counter continues to count until the fifth rising edge is detected on the rx pin. upon detecting the fifth rx edge, the hardware will set the rcif interrupt flag and clear the abden bit of the baudcon register. the rcif flag can be subsequently cleared by reading the rcreg register. the abdovf flag of the baudcon register can be cleared by software directly. to terminate the auto-baud process before the rcif flag is set, clear the abden bit then clear the abdovf bit of the baudcon register. the abdovf bit will remain set if the abden bit is not cleared first. 22.4.3 auto-wake-up on break during sleep mode, all clocks to the eusart are suspended. because of this, the baud rate generator is inactive and a proper character reception cannot be performed. the auto-wake-up feature allows the controller to wake-up due to activity on the rx/dt line. this feature is available only in asynchronous mode. the auto-wake-up feature is enabled by setting the wue bit of the baudcon register. once set, the normal receive sequence on rx/dt is disabled, and the eusart remains in an idle state, monitoring for a wake-up event independent of the cpu mode. a wake-up event consists of a high-to-low transition on the rx/dt line. (this coincides with the start of a sync break or a wake-up signal character for the lin protocol.) the eusart module generates an rcif interrupt coincident with the wake-up event. the interrupt is generated synchronously to the q clocks in normal cpu operating modes ( figure 22-7 ), and asynchronously if the device is in sleep mode ( figure 22-8 ). the interrupt condition is cleared by reading the rcreg register. the wue bit is automatically cleared by the low-to-high transition on the rx line at the end of the break. this signals to the user that the break event is over. at this point, the eusart module is in idle mode waiting to receive the next character. 22.4.3.1 special considerations break character to avoid character errors or character fragments during a wake-up event, the wake-up character must be all zeros. when the wake-up is enabled the function works independent of the low time on the data stream. if the wue bit is set and a valid non-zero character is received, the low time from the start bit to the first rising edge will be interpreted as the wake-up event. the remaining bits in the character will be received as a fragmented character and subsequent characters can result in framing or overrun errors. therefore, the initial character in the transmission must be all ? 0 ?s. this must be ten or more bit times, 13-bit times recommended for lin bus, or any number of bit times for standard rs-232 devices. oscillator start-up time oscillator start-up time must be considered, especially in applications using oscillators with longer start-up intervals (i.e., lp, xt or hs/pll mode). the sync break (or wake-up signal) character must be of sufficient length, and be followed by a sufficient interval, to allow enough time for the selected oscillator to start and provide proper initialization of the eusart. wue bit the wake-up event causes a receive interrupt by setting the rcif bit. the wue bit is cleared in hardware by a rising edge on rx/dt. the interrupt condition is then cleared in software by reading the rcreg register and discarding its contents. to ensure that no actual data is lost, check the rcidl bit to verify that a receive operation is not in process before setting the wue bit. if a receive operation is not occurring, the wue bit may then be set just prior to entering the sleep mode.
? 2011-2013 microchip technology inc. ds40001609b-page 255 pic16(l)f1508/9 figure 22-7: auto-wake-up bit (wue) timing during normal operation figure 22-8: auto-wake-up bit (wue) timings during sleep q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg note 1: the eusart remains in idle while the wue bit is set. q1 q2 q3 q4 q1q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 q1 q2 q3 q4 osc1 wue bit rx/dt line rcif bit set by user auto cleared cleared due to user read of rcreg sleep command executed note 1 note 1: if the wake-up event requires long oscillator warm-up time, the automatic clearing of the wue bit can occur while the stposc signal is still active. this sequence should not depend on the presence of q clocks. 2: the eusart remains in idle while the wue bit is set. sleep ends
pic16(l)f1508/9 ds40001609b-page 256 ? 2011-2013 microchip technology inc. 22.4.4 break character sequence the eusart module has the capability of sending the special break character sequences that are required by the lin bus standard. a break character consists of a start bit, followed by 12 ? 0 ? bits and a stop bit. to send a break character, set the sendb and txen bits of the txsta register. the break character trans- mission is then initiated by a write to the txreg. the value of data written to txreg will be ignored and all ? 0 ?s will be transmitted. the sendb bit is automatically reset by hardware after the corresponding stop bit is sent. this allows the user to preload the transmit fifo with the next transmit byte following the break character (typically, the sync character in the lin specification). the trmt bit of the txsta register indicates when the transmit operation is active or idle, just as it does during normal transmission. see figure 22-9 for the timing of the break character sequence. 22.4.4.1 break and sync transmit sequence the following sequence will start a message frame header made up of a break, followed by an auto-baud sync byte. this sequence is typical of a lin bus master. 1. configure the eusart for the desired mode. 2. set the txen and sendb bits to enable the break sequence. 3. load the txreg with a dummy character to initiate transmission (the value is ignored). 4. write ?55h? to txreg to load the sync character into the transmit fifo buffer. 5. after the break has been sent, the sendb bit is reset by hardware and the sync character is then transmitted. when the txreg becomes empty, as indicated by the txif, the next data byte can be written to txreg. 22.4.5 receiving a break character the enhanced eusart module can receive a break character in two ways. the first method to detect a break character uses the ferr bit of the rcsta register and the received data as indicated by rcreg. the baud rate generator is assumed to have been initialized to the expected baud rate. a break character has been received when; ? rcif bit is set ? ferr bit is set ? rcreg = 00h the second method uses the auto-wake-up feature described in section 22.4.3 ?auto-wake-up on break? . by enabling this feature, the eusart will sample the next two transitions on rx/dt, cause an rcif interrupt, and receive the next data byte followed by another interrupt. note that following a break character, the user will typically want to enable the auto-baud detect feature. for both methods, the user can set the abden bit of the baudcon register before placing the eusart in sleep mode. figure 22-9: send break character sequence write to txreg dummy write brg output (shift clock) start bit bit 0 bit 1 bit 11 stop bit break txif bit (transmit interrupt flag) tx (pin) trmt bit (transmit shift empty flag) sendb (send break control bit) sendb sampled here auto cleared
? 2011-2013 microchip technology inc. ds40001609b-page 257 pic16(l)f1508/9 22.5 eusart synchronous mode synchronous serial communications are typically used in systems with a single master and one or more slaves. the master device contains the necessary cir- cuitry for baud rate generation and supplies the clock for all devices in the system. slave devices can take advantage of the master clock by eliminating the inter- nal clock generation circuitry. there are two signal lines in synchronous mode: a bidi- rectional data line and a clock line. slaves use the external clock supplied by the master to shift the serial data into and out of their respective receive and trans- mit shift registers. since the data line is bidirectional, synchronous operation is half-duplex only. half-duplex refers to the fact that master and slave devices can receive and transmit data but not both simultaneously. the eusart can operate as either a master or slave device. start and stop bits are not used in synchronous trans- missions. 22.5.1 synchronous master mode the following bits are used to configure the eusart for synchronous master operation: ? sync = 1 ? csrc = 1 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. setting the csrc bit of the txsta register configures the device as a master. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 22.5.1.1 master clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device config- ured as a master transmits the clock on the tx/ck line. the tx/ck pin output driver is automatically enabled when the eusart is configured for synchronous transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trail- ing edge of each clock. one clock cycle is generated for each data bit. only as many clock cycles are gener- ated as there are data bits. 22.5.1.2 clock polarity a clock polarity option is provided for microwire compatibility. clock polarity is selected with the sckp bit of the baudcon register. setting the sckp bit sets the clock idle state as high. when the sckp bit is set, the data changes on the falling edge of each clock. clearing the sckp bit sets the idle state as low. when the sckp bit is cleared, the data changes on the rising edge of each clock. 22.5.1.3 synchronous master transmission data is transferred out of the device on the rx/dt pin. the rx/dt and tx/ck pin output drivers are automat- ically enabled when the eusart is configured for syn- chronous master transmit operation. a transmission is initiated by writing a character to the txreg register. if the tsr still contains all or part of a previous character the new character data is held in the txreg until the last bit of the previous character has been transmitted. if this is the first character, or the pre- vious character has been completely flushed from the tsr, the data in the txreg is immediately transferred to the tsr. the transmission of the character com- mences immediately following the transfer of the data to the tsr from the txreg. each data bit changes on the leading edge of the mas- ter clock and remains valid until the subsequent leading clock edge. 22.5.1.4 synchronous master transmission set-up: 1. initialize the spbrgh, spbrgl register pair and the brgh and brg16 bits to achieve the desired baud rate (see section 22.4 ?eusart baud rate generator (brg)? ). 2. enable the synchronous master serial port by setting bits sync, spen and csrc. 3. disable receive mode by clearing bits sren and cren. 4. enable transmit mode by setting the txen bit. 5. if 9-bit transmission is desired, set the tx9 bit. 6. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 7. if 9-bit transmission is selected, the ninth bit should be loaded in the tx9d bit. 8. start transmission by loading data to the txreg register. note: the tsr register is not mapped in data memory, so it is not available to the user.
pic16(l)f1508/9 ds40001609b-page 258 ? 2011-2013 microchip technology inc. figure 22-10: synchronous transmission figure 22-11: synchronous transmis sion (through txen) table 22-7: summary of registers as sociated with synchronous master transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcsta spen rx9 sren cren adden ferr oerr rx9d 246 spbrgl brg<7:0> 248 * spbrgh brg<15:8> 248 * trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txreg eusart transmit data register 237 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous master transmission. * page provides register information. bit 0 bit 1 bit 7 word 1 bit 2 bit 0 bit 1 bit 7 rx/dt write to txreg reg txif bit (interrupt flag) txen bit ? 1 ? ? 1 ? word 2 trmt bit write word 1 write word 2 note: sync master mode, spbrgl = 0 , continuous transmission of two 8-bit words. pin tx/ck pin tx/ck pin (sckp = 0 ) (sckp = 1 ) rx/dt pin tx/ck pin write to txreg reg txif bit trmt bit bit 0 bit 1 bit 2 bit 6 bit 7 txen bit
? 2011-2013 microchip technology inc. ds40001609b-page 259 pic16(l)f1508/9 22.5.1.5 synchronous master reception data is received at the rx/dt pin. the rx/dt pin output driver is automatically disabled when the eusart is configured for synchronous master receive operation. in synchronous mode, reception is enabled by setting either the single receive enable bit (sren of the rcsta register) or the continuous receive enable bit (cren of the rcsta register). when sren is set and cren is clear, only as many clock cycles are generated as there are data bits in a single character. the sren bit is automatically cleared at the completion of one character. when cren is set, clocks are continuously generated until cren is cleared. if cren is cleared in the middle of a character the ck clock stops immediately and the partial charac- ter is discarded. if sren and cren are both set, then sren is cleared at the completion of the first character and cren takes precedence. to initiate reception, set either sren or cren. data is sampled at the rx/dt pin on the trailing edge of the tx/ck clock pin and is shifted into the receive shift register (rsr). when a complete character is received into the rsr, the rcif bit is set and the char- acter is automatically transferred to the two character receive fifo. the least significant eight bits of the top character in the receive fifo are available in rcreg. the rcif bit remains set as long as there are unread characters in the receive fifo. 22.5.1.6 slave clock synchronous data transfers use a separate clock line, which is synchronous with the data. a device configured as a slave receives the clock on the tx/ck line. the tx/ck pin output driver is automatically disabled when the device is configured for synchronous slave transmit or receive operation. serial data bits change on the leading edge to ensure they are valid at the trailing edge of each clock. one data bit is transferred for each clock cycle. only as many clock cycles should be received as there are data bits. 22.5.1.7 receive overrun error the receive fifo buffer can hold two characters. an overrun error will be generated if a third character, in its entirety, is received before rcreg is read to access the fifo. when this happens the oerr bit of the rcsta register is set. previous data in the fifo will not be overwritten. the two characters in the fifo buffer can be read, however, no additional characters will be received until the error is cleared. the oerr bit can only be cleared by clearing the overrun condition. if the overrun error occurred when the sren bit is set and cren is clear then the error is cleared by reading rcreg. if the overrun occurred when the cren bit is set then the error condition is cleared by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. 22.5.1.8 receiving 9-bit characters the eusart supports 9-bit character reception. when the rx9 bit of the rcsta register is set the eusart will shift 9-bits into the rsr for each character received. the rx9d bit of the rcsta register is the ninth, and most significant, data bit of the top unread character in the receive fifo. when reading 9-bit data from the receive fifo buffer, the rx9d data bit must be read before reading the eight least significant bits from the rcreg. 22.5.1.9 synchronous master reception set-up: 1. initialize the spbrgh, spbrgl register pair for the appropriate baud rate. set or clear the brgh and brg16 bits, as required, to achieve the desired baud rate. 2. clear the ansel bit for the rx pin (if applicable). 3. enable the synchronous master serial port by setting bits sync, spen and csrc. 4. ensure bits cren and sren are clear. 5. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 6. if 9-bit reception is desired, set bit rx9. 7. start reception by setting the sren bit or for continuous reception, set the cren bit. 8. interrupt flag bit rcif will be set when reception of a character is complete. an interrupt will be generated if the enable bit rcie was set. 9. read the rcsta register to get the ninth bit (if enabled) and determine if any error occurred during reception. 10. read the 8-bit received data by reading the rcreg register. 11. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. note: if the rx/dt function is on an analog pin, the corresponding ansel bit must be cleared for the receiver to function. note: if the device is configured as a slave and the tx/ck function is on an analog pin, the corresponding ansel bit must be cleared.
pic16(l)f1508/9 ds40001609b-page 260 ? 2011-2013 microchip technology inc. figure 22-12: synchronous reception (master mode, sren) table 22-8: summary of registers as sociated with synchronous master reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ? sckp brg16 ? wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcreg eusart receive data register 240 * rcsta spen rx9 sren cren adden ferr oerr rx9d 246 spbrgl brg<7:0> 248 * spbrgh brg<15:8> 248 * trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous master reception. * page provides register information. cren bit rx/dt write to bit sren sren bit rcif bit (interrupt) read rcreg ? 0 ? bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 ? 0 ? note: timing diagram demonstrates sync master mode with bit sren = 1 and bit brgh = 0 . tx/ck pin tx/ck pin pin (sckp = 0 ) (sckp = 1 )
? 2011-2013 microchip technology inc. ds40001609b-page 261 pic16(l)f1508/9 22.5.2 synchronous slave mode the following bits are used to configure the eusart for synchronous slave operation: ? sync = 1 ? csrc = 0 ? sren = 0 (for transmit); sren = 1 (for receive) ? cren = 0 (for transmit); cren = 1 (for receive) ? spen = 1 setting the sync bit of the txsta register configures the device for synchronous operation. clearing the csrc bit of the txsta register configures the device as a slave. clearing the sren and cren bits of the rcsta register ensures that the device is in the transmit mode, otherwise the device will be configured to receive. setting the spen bit of the rcsta register enables the eusart. 22.5.2.1 eusart synchronous slave transmit the operation of the synchronous master and slave modes are identical (see section 22.5.1.3 ?synchronous master transmission? ) , except in the case of the sleep mode. if two words are written to the txreg and then the sleep instruction is executed, the following will occur: 1. the first character will immediately transfer to the tsr register and transmit. 2. the second word will remain in the txreg register. 3. the txif bit will not be set. 4. after the first character has been shifted out of tsr, the txreg register will transfer the second character to the tsr and the txif bit will now be set. 5. if the peie and txie bits are set, the interrupt will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will call the interrupt service routine. 22.5.2.2 synchronous slave transmission set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for the ck pin (if applicable). 3. clear the cren and sren bits. 4. if interrupts are desired, set the txie bit of the pie1 register and the gie and peie bits of the intcon register. 5. if 9-bit transmission is desired, set the tx9 bit. 6. enable transmission by setting the txen bit. 7. if 9-bit transmission is selected, insert the most significant bit into the tx9d bit. 8. start transmission by writing the least significant eight bits to the txreg register. table 22-9: summary of registers associated with synchronous slave transmission name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcsta spen rx9 sren cren adden ferr oerr rx9d 246 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txreg eusart transmit data register 237 * txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous slave transmission. * page provides register information.
pic16(l)f1508/9 ds40001609b-page 262 ? 2011-2013 microchip technology inc. 22.5.2.3 eusart synchronous slave reception the operation of the synchronous master and slave modes is identical ( section 22.5.1.5 ?synchronous master reception? ), with the following exceptions: ? sleep ? cren bit is always set, therefore the receiver is never idle ? sren bit, which is a ?don?t care? in slave mode a character may be received while in sleep mode by setting the cren bit prior to entering sleep. once the word is received, the rsr register will transfer the data to the rcreg register. if the rcie enable bit is set, the interrupt generated will wake the device from sleep and execute the next instruction. if the gie bit is also set, the program will branch to the interrupt vector. 22.5.2.4 synchronous slave reception set-up: 1. set the sync and spen bits and clear the csrc bit. 2. clear the ansel bit for both the ck and dt pins (if applicable). 3. if interrupts are desired, set the rcie bit of the pie1 register and the gie and peie bits of the intcon register. 4. if 9-bit reception is desired, set the rx9 bit. 5. set the cren bit to enable reception. 6. the rcif bit will be set when reception is complete. an interrupt will be generated if the rcie bit was set. 7. if 9-bit mode is enabled, retrieve the most significant bit from the rx9d bit of the rcsta register. 8. retrieve the eight least significant bits from the receive fifo by reading the rcreg register. 9. if an overrun error occurs, clear the error by either clearing the cren bit of the rcsta register or by clearing the spen bit which resets the eusart. table 22-10: summary of registers associated with synchronous slave reception name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page baudcon abdovf rcidl ?sckp brg16 ? wue abden 247 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie1 tmr1gie adie rcie txie ssp1ie ? tmr2ie tmr1ie 77 pir1 tmr1gif adif rcif txif ssp1if ? tmr2if tmr1if 80 rcreg eusart receive data register 240 * rcsta spen rx9 sren cren adden ferr oerr rx9d 246 trisb trisb7 trisb6 trisb5 trisb4 trisb3 trisb2 trisb1 trisb0 116 txsta csrc tx9 txen sync sendb brgh trmt tx9d 245 legend: ? = unimplemented location, read as ? 0 ?. shaded cells are not used for synchronous slave reception. * page provides register information.
? 2011-2013 microchip technology inc. ds40001609b-page 263 pic16(l)f1508/9 23.0 pulse width modulation (pwm) module the pwm module generates a pulse-width modulated signal determined by the duty cycle, period, and reso- lution that are configured by the following registers: ?pr2 ?t2con ? pwmxdch ? pwmxdcl ?pwmxcon figure 23-1 shows a simplified block diagram of pwm operation. for a step-by-step procedure on how to set up this module for pwm operation, refer to section 23.1.9 ?setup for pwm operation using pwmx pins? . figure 23-1: simplified pwm block diagram 8-bit timer is concatenated with two bits generated by fosc or two bits of the internal prescaler to create 10-bit time-base. note 1: pwmxdch duty cycle registers pwmxdcl<7:6> 10-bit latch (not visible to user) comparator comparator pr2 (1) tmr2 tmr2 module 0 1 pwmxpol pwmx pwmx_out to peripherals r tris control pwmxoe r s q q t2_match rev. 10-000022a_a0
pic16(l)f1508/9 ds40001609b-page 264 ? 2011-2013 microchip technology inc. 23.1 pwmx pin configuration all pwm outputs are multiplexed with the port data latch. the user must configure the pins as outputs by clearing the associated tris bits. 23.1.1 fundamental operation the pwm module produces a 10-bit resolution output. timer2 and pr2 set the period of the pwm. the pwmxdcl and pwmxdch registers configure the duty cycle. the period is common to all pwm modules, whereas the duty cycle is independently controlled. all pwm outputs associated with timer2 are set when tmr2 is cleared. each pwmx is cleared when tmr2 is equal to the value specified in the corresponding pwmxdch (8 msb) and pwmxdcl<7:6> (2 lsb) reg- isters. when the value is greater than or equal to pr2, the pwm output is never cleared (100% duty cycle). 23.1.2 pwm output polarity the output polarity is inverted by setting the pwmxpol bit of the pwmxcon register. 23.1.3 pwm period the pwm period is specified by the pr2 register of timer2. the pwm period can be calculated using the formula of equation 23-1 . equation 23-1: pwm period when tmr2 is equal to pr2, the following three events occur on the next increment cycle: ?tmr2 is cleared ? the pwm output is active. (exception: when the pwm duty cycle = 0%, the pwm output will remain inactive.) ? the pwmxdch and pwmxdcl register values are latched into the buffers. 23.1.4 pwm duty cycle the pwm duty cycle is specified by writing a 10-bit value to the pwmxdch and pwmxdcl register pair. the pwmxdch register contains the eight msbs and the pwmxdcl<7:6>, the two lsbs. the pwmxdch and pwmxdcl registers can be written to at any time. equation 23-2 is used to calculate the pwm pulse width. equation 23-3 is used to calculate the pwm duty cycle ratio. equation 23-2: pulse width equation 23-3: duty cycle ratio the 8-bit timer tmr2 register is concatenated with the two least significant bits of 1/f osc , adjusted by the timer2 prescaler to create the 10-bit time base. the system clock is used if the timer2 prescaler is set to 1:1. figure 23-2 shows a waveform of the pwm signal when the duty cycle is set for the smallest possible pulse. figure 23-2: pwm output note: clearing the pwmxoe bit will relinquish control of the pwmx pin. note: the timer2 postscaler is not used in the determination of the pwm frequency. the postscaler could be used to have a servo update rate at a different frequency than the pwm output. note: the pwmxdch and pwmxdcl registers are double buffered. the buffers are updated when timer2 matches pr2. care should be taken to update both registers before the timer match occurs. pwm period pr2 ?? 1 + ?? 4t osc ? ? ? = (tmr2 prescale value) note: t osc = 1/f osc note: the timer2 postscaler has no effect on the pwm operation. pulse width pwm x dch:pwmxdcl<7:6> ?? ? = t osc ? (tmr2 prescale value) note: t osc = 1/f osc duty cycle ratio pwm x dch:pwmxdcl<7:6> ?? 4 pr2 1 + ?? ----------------------------------------------------------------------------------- = pulse width tmr2 = pr2 tmr2 = 0 tmr2 = pwmxdc f osc pwm q1 q2 q3 q4 rev. 10-000023a_a0
? 2011-2013 microchip technology inc. ds40001609b-page 265 pic16(l)f1508/9 23.1.5 pwm resolution the resolution determines the number of available duty cycles for a given period. for example, a 10-bit resolu- tion will result in 1024 discrete duty cycles, whereas an 8-bit resolution will result in 256 discrete duty cycles. the maximum pwm resolution is ten bits when pr2 is 255. the resolution is a function of the pr2 register value as shown by equation 23-4 . equation 23-4: pwm resolution 23.1.6 operation in sleep mode in sleep mode, the tmr2 register will not increment and the state of the module will not change. if the pwmx pin is driving a value, it will continue to drive that value. when the device wakes up, tmr2 will continue from its previous state. 23.1.7 changes in system clock frequency the pwm frequency is derived from the system clock frequency (f osc ). any changes in the system clock fre- quency will result in changes to the pwm frequency. refer to section 5.0 ?oscillator module (with fail-safe clock monitor)? for additional details. 23.1.8 effects of reset any reset will force all ports to input mode and the pwm registers to their reset states. note: if the pulse width value is greater than the period the assigned pwm pin(s) will remain unchanged. resolution 4pr2 1 + ?? ?? log 2 ?? log ----------------------------------------- - bits = table 23-1: example pwm frequencies and resolutions (f osc = 20 mhz) pwm frequency 0.31 khz 4.88 khz 19.53 khz 78.12 khz 156.3 khz 208.3 khz timer prescale 64 4 1 1 1 1 pr2 value 0xff 0xff 0xff 0x3f 0x1f 0x17 maximum resolution (bits) 10 10 10 8 7 6.6 table 23-2: example pwm frequencies and resolutions (f osc = 8 mhz) pwm frequency 0.31 khz 4.90 khz 19.61 khz 76.92 khz 153.85 khz 200.0 khz timer prescale 64 4 1 1 1 1 pr2 value 0x65 0x65 0x65 0x19 0x0c 0x09 maximum resolution (bits) 8 8 8 6 5 5
pic16(l)f1508/9 ds40001609b-page 266 ? 2011-2013 microchip technology inc. 23.1.9 setup for pwm operation using pwmx pins the following steps should be taken when configuring the module for pwm operation using the pwmx pins: 1. disable the pwmx pin output driver(s) by setting the associated tris bit(s). 2. clear the pwmxcon register. 3. load the pr2 register with the pwm period value. 4. clear the pwmxdch register and bits <7:6> of the pwmxdcl register. 5. configure and start timer2: ? clear the tmr2if interrupt flag bit of the pir1 register. see note below. ? configure the t2ckps bits of the t2con register with the timer2 prescale value. ? enable timer2 by setting the tmr2on bit of the t2con register. 6. enable pwm output pin and wait until timer2 overflows, tmr2if bit of the pir1 register is set. see note below. 7. enable the pwmx pin output driver(s) by clear- ing the associated tris bit(s) and setting the pwmxoe bit of the pwmxcon register. 8. configure the pwm module by loading the pwmxcon register with the appropriate values. note 1: in order to send a complete duty cycle and period on the first pwm output, the above steps must be followed in the order given. if it is not critical to start with a complete pwm signal, then move step 8 to replace step 4. 2: for operation with other peripherals only, disable pwmx pin outputs.
? 2011-2013 microchip technology inc. ds40001609b-page 267 pic16(l)f1508/9 23.2 register definitions: pwm control register 23-1: pwmxcon: pwm control register r/w-0/0 r/w-0/0 r-0/0 r/w-0/0 u-0 u-0 u-0 u-0 pwmxen pwmxoe pwmxout pwmxpol ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 pwmxen: pwm module enable bit 1 = pwm module is enabled 0 = pwm module is disabled bit 6 pwmxoe: pwm module output enable bit 1 = output to pwmx pin is enabled 0 = output to pwmx pin is disabled bit 5 pwmxout: pwm module output value bit bit 4 pwmxpol: pwmx output polarity select bit 1 = pwm output is active low 0 = pwm output is active high bit 3-0 unimplemented: read as ? 0 ?
pic16(l)f1508/9 ds40001609b-page 268 ? 2011-2013 microchip technology inc. register 23-2: pwmxdch: pwm duty cycle high bits r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u pwmxdch<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 pwmxdch<7:0>: pwm duty cycle most significant bits these bits are the msbs of the pwm duty cycle. the two lsbs are found in the pwmxdcl register. register 23-3: pwmxdcl: pwm duty cycle low bits r/w-x/u r/w-x/u u-0 u-0 u-0 u-0 u-0 u-0 pwmxdcl<7:6> ? ? ? ? ? ? bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-6 pwmxdcl<7:6>: pwm duty cycle least significant bits these bits are the lsbs of the pwm duty cycle. the msbs are found in the pwmxdch register. bit 5-0 unimplemented: read as ? 0 ? table 23-3: summary of registers associated with pwm name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page pr2 timer2 module period register 175 * pwm1con pwm1en pwm1oe pwm1out pwm1pol ? ? ? ? 267 pwm1dch pwm1dch<7:0> 268 pwm1dcl pwm1dcl<7:6> ? ? ? ? ? ? 268 pwm2con pwm2en pwm2oe pwm2out pwm2pol ? ? ? ? 267 pwm2dch pwm2dch<7:0> 268 pwm2dcl pwm2dcl<7:6> ? ? ? ? ? ? 268 pwm3con pwm3en pwm3oe pwm3out pwm3pol ? ? ? ? 267 pwm3dch pwm3dch<7:0> 268 pwm3dcl pwm3dcl<7:6> ? ? ? ? ? ? 268 pwm4con pwm4en pwm4oe pwm4out pwm4pol ? ? ? ? 267 pwm4dch pwm4dch<7:0> 268 pwm4dcl pwm4dcl<7:6> ? ? ? ? ? ? 268 t2con ? t2outps<3:0> tmr2on t2ckps<1:0> 177 tmr2 timer2 module register 175 * trisa ? ? trisa5 trisa4 ?(1) trisa2 trisa1 trisa0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: - = unimplemented locations, read as ? 0 ?, u = unchanged, x = unknown. shaded cells are not used by the pwm. * page provides register information. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 269 pic16(l)f1508/9 24.0 configurable logic cell (clc) the configurable logic cell (clcx) provides program- mable logic that operates outside the speed limitations of software execution. the logic cell takes up to 16 input signals, and through the use of configurable gates, reduces the 16 inputs to four logic lines that drive one of eight selectable single-output logic functions. input sources are a combination of the following: ? i/o pins ? internal clocks ? peripherals ? register bits the output can be directed internally to peripherals and to an output pin. refer to figure 24-1 for a simplified diagram showing signal flow through the clcx. possible configurations include: ? combinatorial logic -and -nand - and-or - and-or-invert -or-xor -or-xnor ? latches -s-r - clocked d with set and reset - transparent d with set and reset - clocked j-k with reset figure 24-1: clcx simp lified block diagram input data selection gates (1) logic function (2) lcxg2 lcxg1 lcxg3 lcxg4 lcxmode<2:0> lcxq lcxen lcx_in[0] lcx_in[1] lcx_in[2] lcx_in[3] lcx_in[4] lcx_in[5] lcx_in[6] lcx_in[7] lcx_in[8] lcx_in[9] lcx_in[10] lcx_in[11] lcx_in[12] lcx_in[13] lcx_in[14] lcx_in[15] lcxpol det interrupt det interrupt set bit clcxif lcxintn lcxintp lcxoe tris control clcx to peripherals q1 lcx_out lcxout mlcxout dq rev. 10-000025a_a1 note 1: see figure 24-2 , input data selection and gating. 2: see figure 24-3 , programmable logic functions.
pic16(l)f1508/9 ds40001609b-page 270 ? 2011-2013 microchip technology inc. 24.1 clcx setup programming the clcx module is performed by config- uring the four stages in the logic signal flow. the four stages are: ?data selection ? data gating ? logic function selection ? output polarity each stage is setup at run time by writing to the corre- sponding clcx special function registers. this has the added advantage of permitting logic reconfiguration on-the-fly during program execution. 24.1.1 data selection there are 16 signals available as inputs to the configu- rable logic. four 8-input multiplexers are used to select the inputs to pass on to the next stage. the 16 inputs to the multiplexers are arranged in groups of four. each group is available to two of the four multiplexers, in each case, paired with a different group. this arrange- ment makes possible selection of up to two from a group without precluding a selection from another group. data selection is through four multiplexers as indicated on the left side of figure 24-2 . data inputs in the figure are identified by a generic numbered input name. table 24-1 correlates the generic input name to the actual signal for each clc module. the columns labeled lcxd1 through lcxd4 indicate the mux output for the selected data input. d1s through d4s are abbreviations for the mux select input codes: lcxd1s<2:0> through lcxd4s<2:0>, respectively. selecting a data input in a column excludes all other inputs in that column. data inputs are selected with clcxsel0 and clcxsel1 registers ( register 24-3 and register 24-5 , respectively). note: data selections are undefined at power-up. table 24-1: clcx data input selection data input lcxd1 d1s lcxd2 d2s lcxd3 d3s lcxd4 d4s clc 1clc 2clc 3clc 4 lcx_in[0] 000 ? ? 100 clc1in0 clc2in0 clc3in0 clc4in0 lcx_in[1] 001 ? ? 101 clc1in1 clc2in1 clc3in1 clc4in1 lcx_in[2] 010 ? ? 110 c1out_sync c1out_sync c1out_sync c1out_sync lcx_in[3] 011 ? ? 111 c2out_sync c2out_sync c2out_sync c2out_sync lcx_in[4] 100 000 ? ?f osc f osc f osc f osc lcx_in[5] 101 001 ? ? t0_overflow t0_overflow t0_overflow t0_overflow lcx_in[6] 110 010 ? ? t1_overflow t1_overflow t1_overflow t1_overflow lcx_in[7] 111 011 ? ? t2_match t2_match t2_match t2_match lcx_in[8] ? 100 000 ? lc1_out lc1_out lc1_out lc1_out lcx_in[9] ? 101 001 ? lc2_out lc2_out lc2_out lc2_out lcx_in[10] ? 110 010 ? lc3_out lc3_out lc3_out lc3_out lcx_in[11] ? 111 011 ? lc4_out lc4_out lc4_out lc4_out lcx_in[12] ? ? 100 000 nco1_out lfintosc tx_out (eusart) sck_output (mssp) lcx_in[13] ? ? 101 001 hfintosc frc lfintosc sdo_output (mssp) lcx_in[14] ? ? 110 010 pwm3_out pwm1_out pwm2_out pwm1_out lcx_in[15] ? ? 111 011 pwm4_out pwm2_out pwm3_out pwm4_out
? 2011-2013 microchip technology inc. ds40001609b-page 271 pic16(l)f1508/9 24.1.2 data gating outputs from the input multiplexers are directed to the desired logic function input through the data gating stage. each data gate can direct any combination of the four selected inputs. the gate stage is more than just signal direction. the gate can be configured to direct each input signal as inverted or non-inverted data. directed signals are anded together in each gate. the output of each gate can be inverted before going on to the logic function stage. the gating is in essence a 1-to-4 input and/nand/or/nor gate. when every input is inverted and the output is inverted, the gate is an or of all enabled data inputs. when the inputs and output are not inverted, the gate is an and or all enabled inputs. table 24-2 summarizes the basic logic that can be obtained in gate 1 by using the gate logic select bits. the table shows the logic of four input variables, but each gate can be configured to use less than four. if no inputs are selected, the output will be zero or one, depending on the gate output polarity bit. it is possible (but not recommended) to select both the true and negated values of an input. when this is done, the gate output is zero, regardless of the other inputs, but may emit logic glitches (transient-induced pulses). if the output of the channel must be zero or one, the recommended method is to set all gate bits to zero and use the gate polarity bit to set the desired level. data gating is configured with the logic gate select registers as follows: ? gate 1: clcxgls0 ( register 24-5 ) ? gate 2: clcxgls1 ( register 24-6 ) ? gate 3: clcxgls2 ( register 24-7 ) ? gate 4: clcxgls3 ( register 24-8 ) register number suffixes are different than the gate numbers because other variations of this module have multiple gate selections in the same register. data gating is indicated in the right side of figure 24-2 . only one gate is shown in detail. the remaining three gates are configured identically with the exception that the data enables correspond to the enables for that gate. 24.1.3 logic function there are eight available logic functions including: ? and-or ?or-xor ?and ? s-r latch ? d flip-flop with set and reset ? d flip-flop with reset ? j-k flip-flop with reset ? transparent latch with set and reset logic functions are shown in figure 24-3 . each logic function has four inputs and one output. the four inputs are the four data gate outputs of the previous stage. the output is fed to the inversion stage and from there to other peripherals, an output pin, and back to the clcx itself. 24.1.4 output polarity the last stage in the configurable logic cell is the output polarity. setting the lcxpol bit of the clcxcon reg- ister inverts the output signal from the logic stage. changing the polarity while the interrupts are enabled will cause an interrupt for the resulting output transition. note: data gating is undefined at power-up. table 24-2: data gating logic clcxgls0 lcxg1pol gate logic 0x55 1 and 0x55 0 nand 0xaa 1 nor 0xaa 0 or 0x00 0 logic 0 0x00 1 logic 1
pic16(l)f1508/9 ds40001609b-page 272 ? 2011-2013 microchip technology inc. 24.1.5 clcx setup steps the following steps should be followed when setting up the clcx: ? disable clcx by clearing the lcxen bit. ? select desired inputs using clcxsel0 and clcxsel1 registers (see table 24-1 ). ? clear any associated ansel bits. ? set all tris bits associated with inputs. ? clear all tris bits associated with outputs. ? enable the chosen inputs through the four gates using clcxgls0, clcxgls1, clcxgls2, and clcxgls3 registers. ? select the gate output polarities with the lcxpoly bits of the clcxpol register. ? select the desired logic function with the lcxmode<2:0> bits of the clcxcon register. ? select the desired polarity of the logic output with the lcxpol bit of the clcxpol register. (this step may be combined with the previous gate output polarity step). ? if driving a device, set the desired pin pps control register and also clear the tris bit corresponding to that output. ? if interrupts are desired, configure the following bits: - set the lcxintp bit in the clcxcon register for rising event. - set the lcxintn bit in the clcxcon register or falling event. - set the clcxie bit of the associated pie registers. - set the gie and peie bits of the intcon register. ? enable the clcx by setting the lcxen bit of the clcxcon register. 24.2 clcx interrupts an interrupt will be generated upon a change in the output value of the clcx when the appropriate interrupt enables are set. a rising edge detector and a falling edge detector are present in each clc for this purpose. the clcxif bit of the associated pir registers will be set when either edge detector is triggered and its asso- ciated enable bit is set. the lcxintp enables rising edge interrupts and the lcxintn bit enables falling edge interrupts. both are located in the clcxcon register. to fully enable the interrupt, set the following bits: ? lcxon bit of the clcxcon register ? clcxie bit of the associated pie registers ? lcxintp bit of the clcxcon register (for a rising edge detection) ? lcxintn bit of the clcxcon register (for a falling edge detection) ? peie and gie bits of the intcon register the clcxif bit of the associated pir registers, must be cleared in software as part of the interrupt service. if another edge is detected while this flag is being cleared, the flag will still be set at the end of the sequence. 24.3 output mirror copies mirror copies of all lcxcon output bits are contained in the clcxdata register. reading this register reads the outputs of all clcs simultaneously. this prevents any reading skew introduced by testing or reading the clcxout bits in the individual clcxcon registers. 24.4 effects of a reset the clcxcon register is cleared to zero as the result of a reset. all other selection and gating values remain unchanged. 24.5 operation during sleep the clc module operates independently from the system clock and will continue to run during sleep, provided that the input sources selected remain active. the hfintosc remains active during sleep when the clc module is enabled and the hfintosc is selected as an input source, regardless of the system clock source selected. in other words, if the hfintosc is simultaneously selected as the system clock and as a clc input source, when the clc is enabled, the cpu will go idle during sleep, but the clc will continue to operate and the hfintosc will remain active. this will have a direct effect on the sleep mode current.
? 2011-2013 microchip technology inc. ds40001609b-page 273 pic16(l)f1508/9 figure 24-2: input data selection and gating lcxg1 lcxg1pol data gate 1 lcxd1g1t lcxg2 lcxg3 lcxg4 data gate 2 data gate 3 data gate 4 lcxd1g1n lcxd2g1t lcxd2g1n lcxd3g1t lcxd3g1n lcxd4g1t lcxd4g1n lcxd1s<4:0> lcxd2s<4:0> lcxd3s<4:0> lcxd4s<4:0> lcx_in[0] lcx_in[31] 00000 11111 data selection note: all controls are undefined at power-up. lcxd1t lcxd1n lcxd2t lcxd2n lcxd3t lcxd3n lcxd4t lcxd4n (same as data gate 1) (same as data gate 1) (same as data gate 1) lcx_in[0] lcx_in[31] 00000 11111 lcx_in[0] lcx_in[31] 00000 11111 lcx_in[0] lcx_in[31] 00000 11111
pic16(l)f1508/9 ds40001609b-page 274 ? 2011-2013 microchip technology inc. figure 24-3: programm able logic functions lcxg1 lcxg2 lcxg3 lcxg4 lcxq lcxg1 lcxg2 lcxg3 lcxg4 lcxq lcxg1 lcxg2 lcxg3 lcxg4 lcxq s r q lcxg1 lcxg2 lcxg3 lcxg4 lcxq dq lcxg1 lcxg2 lcxg3 lcxg4 lcxq s r jq lcxg2 lcxg3 lcxg4 lcxq r lcxg1 k dq lcxg1 lcxg2 lcxg3 lcxg4 lcxq s r dq lcxg1 lcxg3 lcxq r lcxg4 lcxg2 lcxmode<2:0>= 000 lcxmode<2:0>= 010 lcxmode<2:0>= 001 lcxmode<2:0>= 011 lcxmode<2:0>= 100 lcxmode<2:0>= 110 lcxmode<2:0>= 101 lcxmode<2:0>= 111 le and - or or - xor 4-input and s-r latch 1-input d flip-flop with s and r 2-input d flip-flop with r 1-input transparent latch with s and r j-k flip-flop with r
? 2011-2013 microchip technology inc. ds40001609b-page 275 pic16(l)f1508/9 24.6 register definitions: clc control register 24-1: clcxcon: configurable logic cell control register r/w-0/0 u-0 r-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 lcxen ? lcxout lcxintp lcxintn lcxmode<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxen: configurable logic cell enable bit 1 = configurable logic cell is enabled and mixing input signals 0 = configurable logic cell is disabled and has logic zero output bit 6 unimplemented: read as ? 0 ? bit 5 lcxout: configurable logic cell data output bit read-only: logic cell output data, after lcxpol; sampled from lcx_out wire. bit 4 lcxintp: configurable logic cell positive edge going interrupt enable bit 1 = clcxif will be set when a rising edge occurs on lcx_out 0 = clcxif will not be set bit 3 lcxintn: configurable logic cell negative edge going interrupt enable bit 1 = clcxif will be set when a falling edge occurs on lcx_out 0 = clcxif will not be set bit 2-0 lcxmode<2:0>: configurable logic cell functional mode bits 111 = cell is 1-input transparent latch with s and r 110 = cell is j-k flip-flop with r 101 = cell is 2-input d flip-flop with r 100 = cell is 1-input d flip-flop with s and r 011 = cell is s-r latch 010 = cell is 4-input and 001 = cell is or-xor 000 = cell is and-or
pic16(l)f1508/9 ds40001609b-page 276 ? 2011-2013 microchip technology inc. register 24-2: clcxpol: signal polarity control register r/w-0/0 u-0 u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxpol ? ? ? lcxg4pol lcxg3pol lcxg2pol lcxg1pol bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxpol: lcout polarity control bit 1 = the output of the logic cell is inverted 0 = the output of the logic cell is not inverted bit 6-4 unimplemented: read as ? 0 ? bit 3 lcxg4pol: gate 4 output polarity control bit 1 = the output of gate 4 is inverted when applied to the logic cell 0 = the output of gate 4 is not inverted bit 2 lcxg3pol: gate 3 output polarity control bit 1 = the output of gate 3 is inverted when applied to the logic cell 0 = the output of gate 3 is not inverted bit 1 lcxg2pol: gate 2 output polarity control bit 1 = the output of gate 2 is inverted when applied to the logic cell 0 = the output of gate 2 is not inverted bit 0 lcxg1pol: gate 1 output polarity control bit 1 = the output of gate 1 is inverted when applied to the logic cell 0 = the output of gate 1 is not inverted
? 2011-2013 microchip technology inc. ds40001609b-page 277 pic16(l)f1508/9 register 24-3: clcxsel0: multiplexer data 1 and 2 select register u-0 r/w-x/u r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u ? lcxd2s<2:0> (1) ? lcxd1s<2:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-4 lcxd2s<2:0>: input data 2 selection control bits (1) 111 = lcx_in[11] is selected for lcxd2 110 = lcx_in[10] is selected for lcxd2 101 = lcx_in[9] is selected for lcxd2 100 = lcx_in[8] is selected for lcxd2 011 = lcx_in[7] is selected for lcxd2 010 = lcx_in[6] is selected for lcxd2 001 = lcx_in[5] is selected for lcxd2 000 = lcx_in[4] is selected for lcxd2 bit 3 unimplemented: read as ? 0 ? bit 2-0 lcxd1s<2:0>: input data 1 selection control bits (1) 111 = lcx_in[7] is selected for lcxd1 110 = lcx_in[6] is selected for lcxd1 101 = lcx_in[5] is selected for lcxd1 100 = lcx_in[4] is selected for lcxd1 011 = lcx_in[3] is selected for lcxd1 010 = lcx_in[2] is selected for lcxd1 001 = lcx_in[1] is selected for lcxd1 000 = lcx_in[0] is selected for lcxd1 note 1: see table 24-1 for signal names associated with inputs.
pic16(l)f1508/9 ds40001609b-page 278 ? 2011-2013 microchip technology inc. register 24-4: clcxsel1: multiplexer data 3 and 4 select register u-0 r/w-x/u r/w-x/u r/w-x/u u-0 r/w-x/u r/w-x/u r/w-x/u ? lcxd4s<2:0> (1) ? lcxd3s<2:0> (1) bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 unimplemented: read as ? 0 ? bit 6-4 lcxd4s<2:0>: input data 4 selection control bits (1) 111 = lcx_in[3] is selected for lcxd4 110 = lcx_in[2] is selected for lcxd4 101 = lcx_in[1] is selected for lcxd4 100 = lcx_in[0] is selected for lcxd4 011 = lcx_in[15] is selected for lcxd4 010 = lcx_in[14] is selected for lcxd4 001 = lcx_in[13] is selected for lcxd4 000 = lcx_in[12] is selected for lcxd4 bit 3 unimplemented: read as ? 0 ? bit 2-0 lcxd3s<2:0>: input data 3 selection control bits (1) 111 = lcx_in[15] is selected for lcxd3 110 = lcx_in[14] is selected for lcxd3 101 = lcx_in[13] is selected for lcxd3 100 = lcx_in[12] is selected for lcxd3 011 = lcx_in[11] is selected for lcxd3 010 = lcx_in[10] is selected for lcxd3 001 = lcx_in[9] is selected for lcxd3 000 = lcx_in[8] is selected for lcxd3 note 1: see table 24-1 for signal names associated with inputs.
? 2011-2013 microchip technology inc. ds40001609b-page 279 pic16(l)f1508/9 register 24-5: clcxgls0: gate 1 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg1d4t lcxg1d4n lcxg1d3t lcxg1d3n lcxg1d2t lcxg1d2n lcxg1d1t lcxg1d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxg1d4t: gate 1 data 4 true (non-inverted) bit 1 = lcxd4t is gated into lcxg1 0 = lcxd4t is not gated into lcxg1 bit 6 lcxg1d4n: gate 1 data 4 negated (inverted) bit 1 = lcxd4n is gated into lcxg1 0 = lcxd4n is not gated into lcxg1 bit 5 lcxg1d3t: gate 1 data 3 true (non-inverted) bit 1 = lcxd3t is gated into lcxg1 0 = lcxd3t is not gated into lcxg1 bit 4 lcxg1d3n: gate 1 data 3 negated (inverted) bit 1 = lcxd3n is gated into lcxg1 0 = lcxd3n is not gated into lcxg1 bit 3 lcxg1d2t: gate 1 data 2 true (non-inverted) bit 1 = lcxd2t is gated into lcxg1 0 = lcxd2t is not gated into lcxg1 bit 2 lcxg1d2n: gate 1 data 2 negated (inverted) bit 1 = lcxd2n is gated into lcxg1 0 = lcxd2n is not gated into lcxg1 bit 1 lcxg1d1t: gate 1 data 1 true (non-inverted) bit 1 = lcxd1t is gated into lcxg1 0 = lcxd1t is not gated into lcxg1 bit 0 lcxg1d1n: gate 1 data 1 negated (inverted) bit 1 = lcxd1n is gated into lcxg1 0 = lcxd1n is not gated into lcxg1
pic16(l)f1508/9 ds40001609b-page 280 ? 2011-2013 microchip technology inc. register 24-6: clcxgls1: gate 2 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg2d4t lcxg2d4n lcxg2d3t lcxg2d3n lcxg2d2t lcxg2d2n lcxg2d1t lcxg2d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxg2d4t: gate 2 data 4 true (non-inverted) bit 1 = lcxd4t is gated into lcxg2 0 = lcxd4t is not gated into lcxg2 bit 6 lcxg2d4n: gate 2 data 4 negated (inverted) bit 1 = lcxd4n is gated into lcxg2 0 = lcxd4n is not gated into lcxg2 bit 5 lcxg2d3t: gate 2 data 3 true (non-inverted) bit 1 = lcxd3t is gated into lcxg2 0 = lcxd3t is not gated into lcxg2 bit 4 lcxg2d3n: gate 2 data 3 negated (inverted) bit 1 = lcxd3n is gated into lcxg2 0 = lcxd3n is not gated into lcxg2 bit 3 lcxg2d2t: gate 2 data 2 true (non-inverted) bit 1 = lcxd2t is gated into lcxg2 0 = lcxd2t is not gated into lcxg2 bit 2 lcxg2d2n: gate 2 data 2 negated (inverted) bit 1 = lcxd2n is gated into lcxg2 0 = lcxd2n is not gated into lcxg2 bit 1 lcxg2d1t: gate 2 data 1 true (non-inverted) bit 1 = lcxd1t is gated into lcxg2 0 = lcxd1t is not gated into lcxg2 bit 0 lcxg2d1n: gate 2 data 1 negated (inverted) bit 1 = lcxd1n is gated into lcxg2 0 = lcxd1n is not gated into lcxg2
? 2011-2013 microchip technology inc. ds40001609b-page 281 pic16(l)f1508/9 register 24-7: clcxgls2: gate 3 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg3d4t lcxg3d4n lcxg3d3t lcxg3d3n lcxg3d2t lcxg3d2n lcxg3d1t lcxg3d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxg3d4t: gate 3 data 4 true (non-inverted) bit 1 = lcxd4t is gated into lcxg3 0 = lcxd4t is not gated into lcxg3 bit 6 lcxg3d4n: gate 3 data 4 negated (inverted) bit 1 = lcxd4n is gated into lcxg3 0 = lcxd4n is not gated into lcxg3 bit 5 lcxg3d3t: gate 3 data 3 true (non-inverted) bit 1 = lcxd3t is gated into lcxg3 0 = lcxd3t is not gated into lcxg3 bit 4 lcxg3d3n: gate 3 data 3 negated (inverted) bit 1 = lcxd3n is gated into lcxg3 0 = lcxd3n is not gated into lcxg3 bit 3 lcxg3d2t: gate 3 data 2 true (non-inverted) bit 1 = lcxd2t is gated into lcxg3 0 = lcxd2t is not gated into lcxg3 bit 2 lcxg3d2n: gate 3 data 2 negated (inverted) bit 1 = lcxd2n is gated into lcxg3 0 = lcxd2n is not gated into lcxg3 bit 1 lcxg3d1t: gate 3 data 1 true (non-inverted) bit 1 = lcxd1t is gated into lcxg3 0 = lcxd1t is not gated into lcxg3 bit 0 lcxg3d1n: gate 3 data 1 negated (inverted) bit 1 = lcxd1n is gated into lcxg3 0 = lcxd1n is not gated into lcxg3
pic16(l)f1508/9 ds40001609b-page 282 ? 2011-2013 microchip technology inc. register 24-8: clcxgls3: gate 4 logic select register r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u lcxg4d4t lcxg4d4n lcxg4d3t lcxg4d3n lcxg4d2t lcxg4d2n lcxg4d1t lcxg4d1n bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 lcxg4d4t: gate 4 data 4 true (non-inverted) bit 1 = lcxd4t is gated into lcxg4 0 = lcxd4t is not gated into lcxg4 bit 6 lcxg4d4n: gate 4 data 4 negated (inverted) bit 1 = lcxd4n is gated into lcxg4 0 = lcxd4n is not gated into lcxg4 bit 5 lcxg4d3t: gate 4 data 3 true (non-inverted) bit 1 = lcxd3t is gated into lcxg4 0 = lcxd3t is not gated into lcxg4 bit 4 lcxg4d3n: gate 4 data 3 negated (inverted) bit 1 = lcxd3n is gated into lcxg4 0 = lcxd3n is not gated into lcxg4 bit 3 lcxg4d2t: gate 4 data 2 true (non-inverted) bit 1 = lcxd2t is gated into lcxg4 0 = lcxd2t is not gated into lcxg4 bit 2 lcxg4d2n: gate 4 data 2 negated (inverted) bit 1 = lcxd2n is gated into lcxg4 0 = lcxd2n is not gated into lcxg4 bit 1 lcxg4d1t: gate 4 data 1 true (non-inverted) bit 1 = lcxd1t is gated into lcxg4 0 = lcxd1t is not gated into lcxg4 bit 0 lcxg4d1n: gate 4 data 1 negated (inverted) bit 1 = lcxd1n is gated into lcxg4 0 = lcxd1n is not gated into lcxg4
? 2011-2013 microchip technology inc. ds40001609b-page 283 pic16(l)f1508/9 register 24-9: clcdata: clc data output u-0 u-0 u-0 u-0 r-0 r-0 r-0 r-0 ? ? ? ? mlc4out mlc3out mlc2out mlc1out bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3 mlc4out: mirror copy of lc4out bit bit 2 mlc3out: mirror copy of lc3out bit bit 1 mlc2out: mirror copy of lc2out bit bit 0 mlc1out: mirror copy of lc1out bit
pic16(l)f1508/9 ds40001609b-page 284 ? 2011-2013 microchip technology inc. table 24-3: summary of registers associated with clcx name bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 register on page ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 113 anselb ? ? ansb5 ansb4 ? ? ? ? 117 anselc ansc7 ansc6 ? ? ansc3 ansc2 ansc1 ansc0 121 clc1con lc1en lc1oe lc1out lc1 intp lc1intn lc1mode<2:0> 275 clcdata ? ? ? ? ? mlc3out mlc2out mlc1out 283 clc1gls0 lc1g1d4t lc1g1d4n lc1g1d3t lc1g 1d3n lc1g1d2t lc1g1d 2n lc1g1d1t lc1g1d1n 279 clc1gls1 lc1g2d4t lc1g2d4n lc1g2d3t lc1g 2d3n lc1g2d2t lc1g2d 2n lc1g2d1t lc1g2d1n 280 clc1gls2 lc1g3d4t lc1g3d4n lc1g3d3t lc1g 3d3n lc1g3d2t lc1g3d 2n lc1g3d1t lc1g3d1n 281 clc1gls3 lc1g4d4t lc1g4d4n lc1g4d3t lc1g 4d3n lc1g4d2t lc1g4d 2n lc1g4d1t lc1g4d1n 282 clc1pol lc1pol ? ? ? lc1g4pol lc1g3pol l c1g2pol lc1g1pol 276 clc1sel0 ? lc1d2s<2:0> ?lc1d1s<2:0> 277 clc1sel1 ? lc1d4s<2:0> ?lc1d3s<2:0> 278 clc2con lc2en lc2oe lc2out lc2 intp lc2intn lc2mode<2:0> 275 clc2gls0 lc2g1d4t lc2g1d4n lc2g1d3t lc2g 1d3n lc2g1d2t lc2g1d 2n lc2g1d1t lc2g1d1n 279 clc2gls1 lc2g2d4t lc2g2d4n lc2g2d3t lc2g 2d3n lc2g2d2t lc2g2d 2n lc2g2d1t lc2g2d1n 280 clc2gls2 lc2g3d4t lc2g3d4n lc2g3d3t lc2g 3d3n lc2g3d2t lc2g3d 2n lc2g3d1t lc2g3d1n 281 clc2gls3 lc2g4d4t lc2g4d4n lc2g4d3t lc2g 4d3n lc2g4d2t lc2g4d 2n lc2g4d1t lc2g4d1n 282 clc2pol lc2pol ? ? ? lc2g4pol lc2g3pol l c2g2pol lc2g1pol 276 clc2sel0 ? lc2d2s<2:0> ?lc2d1s<2:0> 277 clc2sel1 ? lc2d4s<2:0> ?lc2d3s<2:0> 278 clc3con lc3en lc3oe lc3out lc3 intp lc3intn lc3mode<2:0> 275 clc3gls0 lc3g1d4t lc3g1d4n lc3g1d3t lc3g 1d3n lc3g1d2t lc3g1d 2n lc3g1d1t lc3g1d1n 279 clc3gls1 lc3g2d4t lc3g2d4n lc3g2d3t lc3g 2d3n lc3g2d2t lc3g2d 2n lc3g2d1t lc3g2d1n 280 clc3gls2 lc3g3d4t lc3g3d4n lc3g3d3t lc3g 3d3n lc3g3d2t lc3g3d 2n lc3g3d1t lc3g3d1n 281 clc3gls3 lc3g4d4t lc3g4d4n lc3g4d3t lc3g 4d3n lc3g4d2t lc3g4d 2n lc3g4d1t lc3g4d1n 282 clc3pol lc3pol ? ? ? lc3g4pol lc3g3pol l c3g2pol lc3g1pol 276 clc3sel0 ? lc3d2s<2:0> ?lc3d1s<2:0> 277 clc3sel1 ? lc3d4s<2:0> ?lc3d3s<2:0> 278 clc4con lc4en lc4oe lc4out lc4intp lc4intn lc4mode<2:0> 275 clc4gls0 lc4g1d4t lc4g1d4n lc4g1d3t lc4g 1d3n lc4g1d2t lc4g1d 2n lc4g1d1t lc4g1d1n 279 clc4gls1 lc4g2d4t lc4g2d4n lc4g2d3t lc4g 2d3n lc4g2d2t lc4g2d 2n lc4g2d1t lc4g2d1n 280 clc4gls2 lc4g3d4t lc4g3d4n lc4g3d3t lc4g 3d3n lc4g3d2t lc4g3d 2n lc4g3d1t lc4g3d1n 281 clc4gls3 lc4g4d4t lc4g4d4n lc4g4d3t lc4g 4d3n lc4g4d2t lc4g4d 2n lc4g4d1t lc4g4d1n 282 clc4pol lc4pol ? ? ? lc4g4pol lc4g3pol l c4g2pol lc4g1pol 276 clc4sel0 ? lc4d2s<2:0> ?lc4d1s<2:0> 277 clc4sel1 ? lc4d4s<2:0> ?lc4d3s<2:0> 278 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 pie3 ? ? ? ? clc4ie clc3ie clc2ie clc1ie 79 pir3 ? ? ? ? clc4if clc3if clc2if clc1if 82 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 trisb trisb7 trisb6 trisb5 trisb4 ? ? ? ? 116 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: ? = unimplemented read as ? 0 ?,. shaded cells are not used for clc module. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 285 pic16(l)f1508/9 25.0 numerically controlled oscillator (nco) module the numerically controlled oscillator (ncox) module is a timer that uses the overflow from the addition of an increment value to divide the input frequency. the advantage of the addition method over simple counter driven timer is that the resolution of division does not vary with the divider value. the ncox is most useful for applications that require frequency accuracy and fine resolution at a fixed duty cycle. features of the ncox include: ? 16-bit increment function ? fixed duty cycle (fdc) mode ? pulse frequency (pf) mode ? output pulse width control ? multiple clock input sources ? output polarity control ? interrupt capability figure 25-1 is a simplified block diagram of the ncox module. 25.1 ncox operation the ncox operates by repeatedly adding a fixed value to an accumulator. additions occur at the input clock rate. the accumulator will overflow with a carry periodically, which is the raw ncox output (nco_overflow). this effectively reduces the input clock by the ratio of the addition value to the maximum accumulator value. see equation 25-1 . the ncox output can be further modified by stretching the pulse or toggling a flip-flop. the modified ncox output is then distributed internally to other peripherals and optionally output to a pin. the accumulator overflow also generates an interrupt (nco_interrupt). the ncox period changes in discrete steps to create an average frequency. this output depends on the ability of the receiving circuit (i.e., cwg or external resonant converter circuitry) to average the ncox output to reduce uncertainty. 25.1.1 ncox clock sources clock sources available to the ncox include: ?hfintosc ?f osc ? lc1_out ? clkin pin the ncox clock source is selected by configuring the nxcks<2:0> bits in the ncoxclk register. 25.1.2 accumulator the accumulator is a 20-bit register. read and write access to the accumulator is available through three registers: ? ncoxaccl ? ncoxacch ? ncoxaccu 25.1.3 adder the ncox adder is a full adder, which operates independently from the system clock. the addition of the previous result and the increment value replaces the accumulator value on the rising edge of each input clock. 25.1.4 increment registers the increment value is stored in two 8-bit registers making up a 16-bit increment. in order of lsb to msb they are: ? ncoxincl ? ncoxinch when the nco module is enabled, the ncoxinch should be written first, then the ncoxincl register. writing to the ncoxincl register initiates the incre- ment buffer registers to be loaded simultaneously on the second rising edge of the ncox_clk signal. the registers are readable and writable. the increment registers are double-buffered to allow value changes to be made without first disabling the ncox module. when the nco module is disabled, the increment buffers are loaded immediately after a write to the increment registers. equation 25-1: note: the increment buffer registers are not user-accessible. f overflow nco clock frequency increment value ? 2 n ---------------------------------------------------------------------------------------------------------------- = n = accumulator width in bits
pic16(l)f1508/9 ds40001609b-page 286 ? 2011-2013 microchip technology inc. figure 25-1: numerically contro lled oscillator (ncox) module simplified block diagram nco1clk f osc lcx_out dq tris bit 00 01 10 11 nxcks<1:0> 2 nxoe hfintosc ncoxaccu ncoxacch ncoxaccl ncoxinch ncoxincl incbufh incbufl 20 20 20 16 16 nco_overflow dq q _ sq q _ r 0 1 nxpfm nxpol dq q1 nxout ncox nco_interrupt set bit ncoxif en ripple counter 3 nxpws<2:0> r fixed duty cycle mode circuitry pulse frequency mode circuitry (1) ncox_clk note 1: the increment registers are double-buffered to allow for value changes to be made without first disabling the nco module. the f ull increment value is loaded into the buffer registers on the second rising edge of the ncox_clk signal that occurs immediately after a write to ncoxincl register. the buffers are not user- accessible and are shown here for reference. adder ncox_out to peripherals rev. 10-000028a_a0
? 2011-2013 microchip technology inc. ds40001609b-page 287 pic16(l)f1508/9 25.2 fixed duty cycle (fdc) mode in fixed duty cycle (fdc) mode, every time the accumulator overflows (nco_overflow), the output is toggled. this provides a 50% duty cycle, provided that the increment value remains constant. for more information, see figure 25-2 . the fdc mode is selected by clearing the nxpfm bit in the ncoxcon register. 25.3 pulse frequency (pf) mode in pulse frequency (pf) mode, every time the accumu- lator overflows (nco_overflow), the output becomes active for one or more clock periods. once the clock period expires, the output returns to an inactive state. this provides a pulsed output. the output becomes active on the rising clock edge immediately following the overflow event. for more information, see figure 25-2 . the value of the active and inactive states depends on the polarity bit, nxpol in the ncoxcon register. the pf mode is selected by setting the nxpfm bit in the ncoxcon register. 25.3.1 output pulse width control when operating in pf mode, the active state of the out- put can vary in width by multiple clock periods. various pulse widths are selected with the nxpws<2:0> bits in the ncoxclk register. when the selected pulse width is greater than the accumulator overflow time frame, the output of the ncox operation is indeterminate. 25.4 output polarity control the last stage in the ncox module is the output polar- ity. the nxpol bit in the ncoxcon register selects the output polarity. changing the polarity while the inter- rupts are enabled will cause an interrupt for the result- ing output transition. the ncox output can be used internally by source code or other peripherals. accomplish this by reading the nxout (read-only) bit of the ncoxcon register. the ncox output signal is available to the following peripherals: ?clc ?cwg 25.5 interrupts when the accumulator overflows (nco_overflow), the ncox interrupt flag bit, ncoxif, of the pirx register is set. to enable the interrupt event (nco_interrupt), the following bits must be set: ? nxen bit of the ncoxcon register ? ncoxie bit of the piex register ? peie bit of the intcon register ? gie bit of the intcon register the interrupt must be cleared by software by clearing the ncoxif bit in the interrupt service routine. 25.6 effects of a reset all of the ncox registers are cleared to zero as the result of a reset. 25.7 operation in sleep the nco module operates independently from the system clock and will continue to run during sleep, provided that the clock source selected remains active. the hfintosc remains active during sleep when the nco module is enabled and the hfintosc is selected as the clock source, regardless of the system clock source selected. in other words, if the hfintosc is simultaneously selected as the system clock and the nco clock source, when the nco is enabled, the cpu will go idle during sleep, but the nco will continue to operate and the hfintosc will remain active. this will have a direct effect on the sleep mode current. 25.8 alternate pin locations this module incorporates i/o pins that can be moved to other locations with the use of the alternate pin function register, apfcon. to determine which pins can be moved and what their default locations are upon a reset, see section 11.1 ?alternate pin function? for more information.
pic16(l)f1508/9 ds40001609b-page 288 ? 2011-2013 microchip technology inc. figure 25-2: nco ? fixed duty cycl e (fdc) and pulse frequency mode (pfm) output operation diagram 00000h 04000h 08000h fc000h 00000h 04000h 08000h fc000h 00000h 04000h 08000h 4000h 4000h 4000h nco_interrupt ncox output fdc mode ncox output pf mode ncoxpws = ncox output pf mode ncoxpws = ncox accumulator value ncox increment value ncox clock source 000 001 nco_overflow rev. 10-000029a_a0
? 2011-2013 microchip technology inc. ds40001609b-page 289 pic16(l)f1508/9 25.9 register definitions: ncox control registers register 25-2: ncoxclk: ncox input clock control register register 25-1: ncoxcon: ncox control register r/w-0/0 r/w-0/0 r-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 nxen nxoe nxout nxpol ? ? ?nxpfm bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7 nxen: ncox enable bit 1 = ncox module is enabled 0 = ncox module is disabled bit 6 nxoe: ncox output enable bit 1 = ncox output pin is enabled 0 = ncox output pin is disabled bit 5 nxout: ncox output bit 1 = ncox output is high 0 = ncox output is low bit 4 nxpol: ncox polarity bit 1 = ncox output signal is active low (inverted) 0 = ncox output signal is active high (non-inverted) bit 3-1 unimplemented : read as ? 0 ? bit 0 nxpfm: ncox pulse frequency mode bit 1 = ncox operates in pulse frequency mode 0 = ncox operates in fixed duty cycle mode r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 nxpws<2:0> (1, 2) ? ? ?nxcks<1:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-5 nxpws<2:0>: ncox output pulse width select bits (1, 2) 111 = 128 ncox clock periods 110 = 64 ncox clock periods 101 = 32 ncox clock periods 100 = 16 ncox clock periods 011 = 8 ncox clock periods 010 = 4 ncox clock periods 001 = 2 ncox clock periods 000 = 1 ncox clock periods bit 4-2 unimplemented: read as ? 0 ? bit 1-0 nxcks<1:0>: ncox clock source select bits 11 = nco1clk pin 10 = lc1_out 01 = f osc 00 = hfintosc (16 mhz) note 1: nxpws applies only when operating in pulse frequency mode. 2: if ncox pulse width is greater than nco_overflow period, operation is undeterminate.
pic16(l)f1508/9 ds40001609b-page 290 ? 2011-2013 microchip technology inc. register 25-3: ncoxaccl: ncox accumulator register ? low byte register 25-4: ncoxacch: ncox accum ulator register ? high byte register 25-5: ncoxaccu: ncox accum ulator register ? upper byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ncoxacc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ncoxacc<7:0>: ncox accumulator, low byte r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ncoxacc<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ncoxacc<15:8>: ncox accumulator, high byte u-0 u-0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ? ? ? ? nco x acc<19:16> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-4 unimplemented: read as ? 0 ? bit 3-0 nco x acc<19:16>: nco x accumulator, upper byte
? 2011-2013 microchip technology inc. ds40001609b-page 291 pic16(l)f1508/9 register 25-6: ncoxincl: ncox increment register ? low byte (1) register 25-7: ncoxinch: ncox increment register ? high byte (1) table 25-1: summary of register s associated with ncox r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-1/1 ncoxinc<7:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ncoxinc<7:0>: ncox increment, low byte note 1: write the ncoxinch register first, then the ncoxincl register. see 25.1.4 ?increment registers? for more information. r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 ncoxinc<15:8> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared bit 7-0 ncoxinc<15:8>: ncox increment, high byte note 1: write the ncoxinch register first, then the ncoxincl register. see 25.1.4 ?increment registers? for more information. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page apfcon ? ? ? sssel t1gsel ? clc1sel nco1sel 110 intcon gie peie tmr0ie inte iocie tmr0if intf iocif 76 nco1acch nco1acc<15:8> 290 nco1accl nco1acc<7:0> 290 nco1accu ? nco1acc<19:16> 290 nco1clk n1pws<2:0> ? ? ?n1cks<1:0> 289 nco1con n1en n1oe n1out n1pol ? ? ?n1pfm 289 nco1inch nco1inc<15:8> 291 nco1incl nco1inc<7:0> 291 pie2 osfie c2ie c1ie ? bcl1ie nco1ie ? ? 78 pir2 osfif c2if c1if ? bcl1if nco1if ? ? 81 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: x = unknown, u = unchanged, ? = unimplemented read as ? 0 ?, q = value depends on condition. shaded cells are not used for ncox module. note 1: unimplemented, read as ? 1 ?.
pic16(l)f1508/9 ds40001609b-page 292 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 293 pic16(l)f1508/9 26.0 complementary waveform generator (cwg) module the complementary waveform generator (cwg) produces a complementary waveform with dead-band delay from a selection of input sources. the cwg module has the following features: ? selectable dead-band clock source control ? selectable input sources ? output enable control ? output polarity control ? dead-band control with independent 6-bit rising and falling edge dead-band counters ? auto-shutdown control with: - selectable shutdown sources - auto-restart enable - auto-shutdown pin override control 26.1 fundamental operation the cwg generates two output waveforms from the selected input source. the off-to-on transition of each output can be delayed from the on-to-off transition of the other output, thereby, creating a time delay immediately where neither output is driven. this is referred to as dead time and is covered in section 26.5 ?dead-band control? . a typical operating waveform, with dead band, generated from a single input signal is shown in figure 26-2 . it may be necessary to guard against the possibility of circuit faults or a feedback event arriving too late or not at all. in this case, the active drive must be terminated before the fault condition causes damage. this is referred to as auto-shutdown and is covered in section 26.9 ?auto-shutdown control? . 26.2 clock source the cwg module allows the following clock sources to be selected: ? fosc (system clock) ? hfintosc (16 mhz only) the clock sources are selected using the g1cs0 bit of the cwgxcon0 register ( register 26-1 ). 26.3 selectable input sources the cwg generates the output waveforms from the input sources in tab l e 2 6- 1 . the input sources are selected using the gxis<2:0> bits in the cwgxcon1 register ( register 26-2 ). 26.4 output control immediately after the cwg module is enabled, the complementary drive is configured with both cwgxa and cwgxb drives cleared. 26.4.1 output enables each cwg output pin has individual output enable control. output enables are selected with the gxoea and gxoeb bits of the cwgxcon0 register. when an output enable control is cleared, the module asserts no control over the pin. when an output enable is set, the override value or active pwm waveform is applied to the pin per the port priority selection. the output pin enables are dependent on the module enable bit, gxen. when gxen is cleared, cwg output enables and cwg drive levels have no effect. 26.4.2 polarity control the polarity of each cwg output can be selected independently. when the output polarity bit is set, the corresponding output is active-high. clearing the output polarity bit configures the corresponding output as active-low. however, polarity does not affect the override levels. output polarity is selected with the gxpola and gxpolb bits of the cwgxcon0 register. table 26-1: selectable input sources source peripheral signal name comparator c1 c1out_sync comparator c2 c2out_sync pwm1 pwm1_out pwm2 pwm2_out pwm3 pwm3_out pwm4 pwm4_out nco1 nco1_out clc1 lc1_out
pic16(l)f1508/9 ds40001609b-page 294 ? 2011-2013 microchip technology inc. figure 26-1: simplifi ed cwg block diagram cwg_clock gxcs input source pwm1_out pwm2_out nco1_out cwg1flt (int pin) gxasdflt lc2_out gxasclc f osc hfintosc gxis lc1_out auto-shutdown source g x pola 1 3 q s rq en r gxarsen cwgxdbr g x polb 6 cwgxdbf 0 1 0 1 00 10 11 ? 0 ? ? 1 ? 00 10 11 ? 0 ? ? 1 ? g x asdlb 2 gxasdla 2 cwg x a cwg x b gxasdla = 01 gxasdlb = 01 gxase gxoea gxoeb = en r 6 = trisx trisx x = cwg module number pwm3_out pwm4_out q s rq q d s write gxase data bit shutdown set dominate c1out_async c2out_async c2out_async gxasdc2 c1out_async gxasdc1
? 2011-2013 microchip technology inc. ds40001609b-page 295 pic16(l)f1508/9 figure 26-2: typical cwg operatio n with pwm1 (no auto-shutdown) 26.5 dead-band control dead-band control provides for non-overlapping output signals to prevent shoot-through current in power switches. the cwg contains two 6-bit dead-band counters. one dead-band counter is used for the rising edge of the input source control. the other is used for the falling edge of the input source control. dead band is timed by counting cwg clock periods from zero up to the value in the rising or falling dead- band counter registers. see cwgxdbr and cwgxdbf registers ( register 26-4 and register 26-5 , respectively). 26.6 rising edge dead band the rising edge dead-band delays the turn-on of the cwgxa output from when the cwgxb output is turned off. the rising edge dead-band time starts when the rising edge of the input source signal goes true. when this happens, the cwgxb output is immediately turned off and the rising edge dead-band delay time starts. when the rising edge dead-band delay time is reached, the cwgxa output is turned on. the cwgxdbr register sets the duration of the dead- band interval on the rising edge of the input source signal. this duration is from 0 to 64 counts of dead band. dead band is always counted off the edge on the input source signal. a count of 0 (zero), indicates that no dead band is present. if the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. 26.7 falling edge dead band the falling edge dead band delays the turn-on of the cwgxb output from when the cwgxa output is turned off. the falling edge dead-band time starts when the falling edge of the input source goes true. when this happens, the cwgxa output is immediately turned off and the falling edge dead-band delay time starts. when the falling edge dead-band delay time is reached, the cwgxb output is turned on. the cwgxdbf register sets the duration of the dead- band interval on the falling edge of the input source sig- nal. this duration is from 0 to 64 counts of dead band. dead band is always counted off the edge on the input source signal. a count of 0 (zero), indicates that no dead band is present. if the input source signal is not present for enough time for the count to be completed, no output will be seen on the respective output. refer to figure 26-3 and figure 26-4 for examples. rising edge d falling edge dead band rising edge dead band falling edge dead band cwg_clock pwm1 cwgxa cwgxb rising edge dead band
pic16(l)f1508/9 ds40001609b-page 296 ? 2011-2013 microchip technology inc. figure 26-3: dead-band operation, cwgxdbr = 01h, cwgxdbf = 02h figure 26-4: dead-band operation, cwgxdbr = 03h, cwgxdbf = 04h, source shorter than dead band input source cwgxa cwgxb cwg_clock source shorter than dead band input source cwgxa cwgxb cwg_clock
? 2011-2013 microchip technology inc. ds40001609b-page 297 pic16(l)f1508/9 26.8 dead-band uncertainty when the rising and falling edges of the input source triggers the dead-band counters, the input may be asyn- chronous. this will create some uncertainty in the dead- band time delay. the maximum uncertainty is equal to one cwg clock period. refer to equation 26-1 for more detail. equation 26-1: dead-band uncertainty 26.9 auto-shutdown control auto-shutdown is a method to immediately override the cwg output levels with specific overrides that allow for safe shutdown of the circuit. the shutdown state can be either cleared automatically or held until cleared by software. 26.9.1 shutdown the shutdown state can be entered by either of the following two methods: ? software generated ? external input 26.9.1.1 software generated shutdown setting the gxase bit of the cwgxcon2 register will force the cwg into the shutdown state. when auto-restart is disabled, the shutdown state will persist as long as the gxase bit is set. when auto-restart is enabled, the gxase bit will clear automatically and resume operation on the next rising edge event. see figure 26-6 . 26.9.1.2 external input source external shutdown inputs provide the fastest way to safely suspend cwg operation in the event of a fault condition. when any of the selected shutdown inputs goes active, the cwg outputs will immediately go to the selected override levels without software delay. any combination of two input sources can be selected to cause a shutdown condition. the sources are: ? comparator c1 ? c1out_async ? comparator c2 ? c2out_async ? clc2 ? lc2_out ? cwg1flt shutdown inputs are selected using the gxasds0 and gxasds1 bits of the cwgxcon2 register. ( register 26-3 ). t deadband _ uncertainty 1 fcwg_clock ---------------------------- - = therefore: fcwg_clock 16 mhz = 1 16 mhz ------------------ - = 62.5ns = t deadband _ uncertainty 1 fcwg_clock ---------------------------- - = example: note: shutdown inputs are level sensitive, not edge sensitive. the shutdown state can- not be cleared, except by disabling auto- shutdown, as long as the shutdown input level persists.
pic16(l)f1508/9 ds40001609b-page 298 ? 2011-2013 microchip technology inc. 26.10 operation during sleep the cwg module operates independently from the system clock and will continue to run during sleep, provided that the clock and input sources selected remain active. the hfintosc remains active during sleep, provided that the cwg module is enabled, the input source is active, and the hfintosc is selected as the clock source, regardless of the system clock source selected. in other words, if the hfintosc is simultaneously selected as the system clock and the cwg clock source, when the cwg is enabled and the input source is active, the cpu will go idle during sleep, but the cwg will continue to operate and the hfintosc will remain active. this will have a direct effect on the sleep mode current. 26.11 configuring the cwg the following steps illustrate how to properly configure the cwg to ensure a synchronous start: 1. ensure that the tris control bits corresponding to cwgxa and cwgxb are set so that both are configured as inputs. 2. clear the gxen bit, if not already cleared. 3. set desired dead-band times with the cwgxdbr and cwgxdbf registers. 4. setup the following controls in cwgxcon2 auto-shutdown register: ? select desired shutdown source. ? select both output overrides to the desired levels (this is necessary even if not using auto-shutdown because start-up will be from a shutdown state). ? set the gxase bit and clear the gxarsen bit. 5. select the desired input source using the cwgxcon1 register. 6. configure the following controls in cwgxcon0 register: ? select desired clock source. ? select the desired output polarities. ? set the output enables for the outputs to be used. 7. set the gxen bit. 8. clear tris control bits corresponding to cwgxa and cwgxb to be used to configure those pins as outputs. 9. if auto-restart is to be used, set the gxarsen bit and the gxase bit will be cleared automati- cally. otherwise, clear the gxase bit to start the cwg. 26.11.1 pin override levels the levels driven to the output pins, while the shutdown input is true, are controlled by the gxasdla and gxasdlb bits of the cwgxcon2 register ( register 26-3 ). gxasdla controls the cwg1a override level and gxasdlb controls the cwg1b override level. the control bit logic level corresponds to the output logic drive level while in the shutdown state. the polarity control does not apply to the override level. 26.11.2 auto-shutdown restart after an auto-shutdown event has occurred, there are two ways to have resume operation: ? software controlled ? auto-restart the restart method is selected with the gxarsen bit of the cwgxcon2 register. waveforms of software controlled and automatic restarts are shown in figure 26-5 and figure 26-6 . 26.11.2.1 software controlled restart when the gxarsen bit of the cwgxcon2 register is cleared, the cwg must be restarted after an auto-shut- down event by software. clearing the shutdown state requires all selected shut- down inputs to be low, otherwise the gxase bit will remain set. the overrides will remain in effect until the first rising edge event after the gxase bit is cleared. the cwg will then resume operation. 26.11.2.2 auto-restart when the gxarsen bit of the cwgxcon2 register is set, the cwg will restart from the auto-shutdown state automatically. the gxase bit will clear automatically when all shut- down sources go low. the overrides will remain in effect until the first rising edge event after the gxase bit is cleared. the cwg will then resume operation.
? 2011-2013 microchip technology inc. ds40001609b-page 299 pic16(l)f1508/9 figure 26-5: shutdown functionality, auto-restart disabled (gxarsen = 0, gxasdla = 01 , gxasdlb = 01 ) figure 26-6: shutdown f unctionality, auto-restart enabled (gxarsen = 1, gxasdla = 01 , gxasdlb = 01 ) shutdown g x ase cleared by software output resumes no shutdown cwg input g x ase cwg1a source shutdown source shutdown event ceases tri-state (no pulse) cwg1b tri-state (no pulse) shutdown tri-state (no pulse) g x ase auto-cleared by hardware output resumes no shutdown cwg input g x ase cwg1a source shutdown source shutdown event ceases cwg1b tri-state (no pulse)
pic16(l)f1508/9 ds40001609b-page 300 ? 2011-2013 microchip technology inc. 26.12 register definitions: cwg control register 26-1: cwgxcon0: cwg control register 0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 gxen gxoeb gxoea gxpolb gxpola ? ?gxcs0 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 gxen: cwgx enable bit 1 = module is enabled 0 = module is disabled bit 6 gxoeb: cwgxb output enable bit 1 = cwgxb is available on appropriate i/o pin 0 = cwgxb is not available on appropriate i/o pin bit 5 gxoea: cwgxa output enable bit 1 = cwgxa is available on appropriate i/o pin 0 = cwgxa is not available on appropriate i/o pin bit 4 gxpolb: cwgxb output polarity bit 1 = output is inverted polarity 0 = output is normal polarity bit 3 gxpola: cwgxa output polarity bit 1 = output is inverted polarity 0 = output is normal polarity bit 2-1 unimplemented : read as ? 0 ? bit 0 gxcs0: cwgx clock source select bit 1 =hfintosc 0 =f osc
? 2011-2013 microchip technology inc. ds40001609b-page 301 pic16(l)f1508/9 register 26-2: cwgxcon1: cwg control register 1 r/w-x/u r/w-x/u r/w-x/u r/w-x/u u-0 r/w-0/0 r/w-0/0 r/w-0/0 gxasdlb<1:0> gxasdla<1:0> ? gxis<2:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-6 gxasdlb<1:0>: cwgx shutdown state for cwgxb when an auto shutdown event is present (gxase = 1 ): 11 = cwgxb pin is driven to ? 1 ?, regardless of the setting of the gxpolb bit. 10 = cwgxb pin is driven to ? 0 ?, regardless of the setting of the gxpolb bit. 01 = cwgxb pin is tri-stated 00 = cwgxb pin is driven to its inactive state after the selected dead-band interval. gxpolb still will control the polarity of the output. bit 5-4 gxasdla<1:0>: cwgx shutdown state for cwgxa when an auto shutdown event is present (gxase = 1 ): 11 = cwgxa pin is driven to ? 1 ?, regardless of the setting of the gxpola bit. 10 = cwgxa pin is driven to ? 0 ?, regardless of the setting of the gxpola bit. 01 = cwgxa pin is tri-stated 00 = cwgxa pin is driven to its inactive state after the selected dead-band interval. gxpola still will control the polarity of the output. bit 3 unimplemented: read as ? 0 ? bit 2-0 gxis<2:0>: cwgx input source select bits 111 = clc1 ? lc1_out 110 = nco1 ? nco1_out 101 = pwm4 ? pwm4_out 100 = pwm3 ? pwm3_out 011 = pwm2 ? pwm2_out 010 = pwm1 ? pwm1_out 001 = comparator c1 ? c1out_async 000 = comparator c2 ? c2out_async
pic16(l)f1508/9 ds40001609b-page 302 ? 2011-2013 microchip technology inc. register 26-3: cwgxcon2: cwg control register 2 r/w-0/0 r/w-0/0 u-0 u-0 r/w-0/0 r/w-0/0 r/w-0/0 r/w-0/0 gxase g x arsen ? ? gxasdc2 gxasdc1 gxasdflt gxasdclc2 bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7 gxase: auto-shutdown event status bit 1 = an auto-shutdown event has occurred 0 = no auto-shutdown event has occurred bit 6 gxarsen: auto-restart enable bit 1 = auto-restart is enabled 0 = auto-restart is disabled bit 5-4 unimplemented: read as ? 0 ? bit 3 gxasdc2: cwg auto-shutdown on comparator c2 enable bit 1 = shutdown when comparator c2 output (c2out_async) is high 0 = comparator c2 output has no effect on shutdown bit 2 gxasdc1: cwg auto-shutdown on comparator c1 enable bit 1 = shutdown when comparator c1 output (c1out_async) is high 0 = comparator c1 output has no effect on shutdown bit 1 gxasdflt: cwg auto-shutdown on flt enable bit 1 = shutdown when cwg1flt input is low 0 =cwg1flt input has no effect on shutdown bit 0 gxasdclc2: cwg auto-shutdown on clc2 enable bit 1 = shutdown when clc2 output (lc2_out) is high 0 = clc2 output has no effect on shutdown
? 2011-2013 microchip technology inc. ds40001609b-page 303 pic16(l)f1508/9 register 26-4: cwg x dbr: complementary waveform generator (cwg x) rising dead-band count register register 26-5: cwg x dbf: complementary waveform generator (cwg x) falling dead-band count register u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? cwg x dbr<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as ? 0 ? bit 5-0 cwgxdbr<5:0>: complementary waveform generator (cwgx) rising counts 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band ?? ?? ? 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band u-0 u-0 r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u r/w-x/u ? ? cwgxdbf<5:0> bit 7 bit 0 legend: r = readable bit w = writable bit u = unimplemented bit, read as ?0? u = bit is unchanged x = bit is unknown -n/n = value at por and bor/value at all other resets ?1? = bit is set ?0? = bit is cleared q = value depends on condition bit 7-6 unimplemented: read as ? 0 ? bit 5-0 cwgxdbf<5:0>: complementary waveform generator (cwgx) falling counts 11 1111 = 63-64 counts of dead band 11 1110 = 62-63 counts of dead band ?? ?? ? 00 0010 = 2-3 counts of dead band 00 0001 = 1-2 counts of dead band 00 0000 = 0 counts of dead band. dead-band generation is bypassed.
pic16(l)f1508/9 ds40001609b-page 304 ? 2011-2013 microchip technology inc. table 26-2: summary of registers associated with cwg name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 register on page ansela ? ? ? ansa4 ? ansa2 ansa1 ansa0 113 cwg1con0 g1en g1oeb g1oea g1polb g1pola ? ?g1cs0 300 cwg1con1 g1asdlb<1:0> g1asdla<1:0> ? ? g1is<1:0> 301 cwg1con2 g1ase g1arsen ? ? g1asdc2 g1asdc1 g1asdsflt g1asdsclc2 302 cwg1dbf ? ? cwg1dbf<5:0> 303 cwg1dbr ? ? cwg1dbr<5:0> 303 trisa ? ? trisa5 trisa4 ? (1) trisa2 trisa1 trisa0 112 trisc trisc7 trisc6 trisc5 trisc4 trisc3 trisc2 trisc1 trisc0 120 legend: x = unknown, u = unchanged, ? = unimplemented locations read as ? 0 ?. shaded cells are not used by cwg. note 1: unimplemented, read as ? 1 ?.
? 2011-2013 microchip technology inc. ds40001609b-page 305 pic16(l)f1508/9 27.0 in-circuit serial programming? (icsp?) icsp? programming allows customers to manufacture circuit boards with unprogrammed devices. programming can be done after the assembly process allowing the device to be programmed with the most recent firmware or a custom firmware. five pins are needed for icsp? programming: ? icspclk ? icspdat ?mclr /v pp ?v dd ?v ss in program/verify mode the program memory, user ids and the configuration words are programmed through serial communications. the icspdat pin is a bidirec- tional i/o used for transferring the serial data and the icspclk pin is the clock input. for more information on icsp? refer to the ? pic12(l)f1501/pic16(l)f150x memory programming specification ? (ds41573). 27.1 high-voltage programming entry mode the device is placed into high-voltage programming entry mode by holding the icspclk and icspdat pins low then raising the voltage on mclr /v pp to v ihh . 27.2 low-voltage programming entry mode the low-voltage programming entry mode allows the pic ? flash mcus to be programmed using v dd only, without high voltage. when the lvp bit of configuration words is set to ? 1 ?, the icsp low-voltage programming entry mode is enabled. to disable the low-voltage icsp mode, the lvp bit must be programmed to ? 0 ?. entry into the low-voltage programming entry mode requires the following steps: 1. mclr is brought to v il . 2. a 32-bit key sequence is presented on icspdat, while clocking icspclk. once the key sequence is complete, mclr must be held at v il for as long as program/verify mode is to be maintained. if low-voltage programming is enabled (lvp = 1 ), the mclr reset function is automatically enabled and cannot be disabled. see section 6.5 ?mclr? for more information. the lvp bit can only be reprogrammed to ? 0 ? by using the high-voltage programming mode. 27.3 common programming interfaces connection to a target device is typically done through an icsp? header. a commonly found connector on development tools is the rj-11 in the 6p6c (6-pin, 6-connector) configuration. see figure 27-1 . figure 27-1: icd rj-11 style connector interface another connector often found in use with the pickit? programmers is a standard 6-pin header with 0.1 inch spacing. refer to figure 27-2 . 1 2 3 4 5 6 target bottom side pc board v pp /mclr v ss icspclk v dd icspdat nc pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect
pic16(l)f1508/9 ds40001609b-page 306 ? 2011-2013 microchip technology inc. figure 27-2: pickit? programme r style connector interface for additional interface recommendations, refer to your specific device programmer manual prior to pcb design. it is recommended that isolation devices be used to separate the programming pins from other circuitry. the type of isolation is highly dependent on the specific application and may include devices such as resistors, diodes, or even jumpers. see figure 27-3 for more information. figure 27-3: typical connect ion for icsp? programming 1 2 3 4 5 6 * the 6-pin header (0.100" spacing) accepts 0.025" square pins. pin description* 1 = v pp /mclr 2 = v dd target 3 = v ss (ground) 4 = icspdat 5 = icspclk 6 = no connect pin 1 indicator v dd v pp v ss external device to be data clock v dd mclr /v pp v ss icspdat icspclk * * * to normal connections * isolation devices (as required). programming signals programmed v dd
? 2011-2013 microchip technology inc. ds40001609b-page 307 pic16(l)f1508/9 28.0 instruction set summary each instruction is a 14-bit word containing the opera- tion code (opcode) and all required operands. the opcodes are broken into three broad categories. ? byte oriented ? bit oriented ? literal and control the literal and control category contains the most varied instruction word format. table 28-3 lists the instructions recognized by the mpasm tm assembler. all instructions are executed within a single instruction cycle, with the following exceptions, which may take two or three cycles: ? subroutine takes two cycles ( call , callw ) ? returns from interrupts or subroutines take two cycles ( return , retlw , retfie ) ? program branching takes two cycles ( goto , bra , brw , btfss , btfsc , decfsz , incsfz ) ? one additional instruction cycle will be used when any instruction references an indirect file register and the file select register is pointing to program memory. one instruction cycle consists of 4 oscillator cycles; for an oscillator frequency of 4 mhz, this gives a nominal instruction execution rate of 1 mhz. all instruction examples use the format ? 0xhh ? to represent a hexadecimal number, where ? h ? signifies a hexadecimal digit. 28.1 read-modify-write operations any instruction that specifies a file register as part of the instruction performs a read-modify-write (r-m-w) operation. the register is read, the data is modified, and the result is stored according to either the instruc- tion, or the destination designator ?d?. a read operation is performed on a register even if the instruction writes to that register. table 28-1: opcode field descriptions table 28-2: abbreviation descriptions field description f register file address (0x00 to 0x7f) w working register (accumulator) b bit address within an 8-bit file register k literal field, constant data or label x don?t care location (= 0 or 1 ). the assembler will generate code with x = 0 . it is the recommended form of use for compatibility with all microchip software tools. d destination select; d = 0 : store result in w , d = 1 : store result in file register f. default is d = 1. n fsr or indf number. (0-1) mm pre-post increment-decrement mode selection field description pc program counter to time-out bit c carry bit dc digit carry bit z zero bit pd power-down bit
pic16(l)f1508/9 ds40001609b-page 308 ? 2011-2013 microchip technology inc. figure 28-1: general format for instructions byte-oriented file register operations 13 8 7 6 0 d = 0 for destination w opcode d f (file #) d = 1 for destination f f = 7-bit file register address bit-oriented file register operations 13 10 9 7 6 0 opcode b (bit #) f (file #) b = 3-bit bit address f = 7-bit file register address literal and control operations 13 8 7 0 opcode k (literal) k = 8-bit immediate value 13 11 10 0 opcode k (literal) k = 11-bit immediate value general call and goto instructions only movlp instruction only 13 5 4 0 opcode k (literal) k = 5-bit immediate value movlb instruction only 13 9 8 0 opcode k (literal) k = 9-bit immediate value bra instruction only fsr offset instructions 13 7 6 5 0 opcode n k (literal) n = appropriate fsr fsr increment instructions 13 7 6 0 opcode k (literal) k = 7-bit immediate value 13 3 2 1 0 opcode n m (mode) n = appropriate fsr m = 2-bit mode value k = 6-bit immediate value 13 0 opcode opcode only
? 2011-2013 microchip technology inc. ds40001609b-page 309 pic16(l)f1508/9 table 28-3: pic16(l)f1508/9 instruction set mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb byte-oriented file register operations addwf addwfc andwf asrf lslf lsrf clrf clrw comf decf incf iorwf movf movwf rlf rrf subwf subwfb swapf xorwf f, d f, d f, d f, d f, d f, d f ? f, d f, d f, d f, d f, d f f, d f, d f, d f, d f, d f, d add w and f add with carry w and f and w with f arithmetic right shift logical left shift logical right shift clear f clear w complement f decrement f increment f inclusive or w with f move f move w to f rotate left f through carry rotate right f through carry subtract w from f subtract with borrow w from f swap nibbles in f exclusive or w with f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 00 11 00 11 11 11 00 00 00 00 00 00 00 00 00 00 00 11 00 00 0111 1101 0101 0111 0101 0110 0001 0001 1001 0011 1010 0100 1000 0000 1101 1100 0010 1011 1110 0110 dfff dfff dfff dfff dfff dfff lfff 0000 dfff dfff dfff dfff dfff 1fff dfff dfff dfff dfff dfff dfff ffff ffff ffff ffff ffff ffff ffff 00xx ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff c, dc, z c, dc, z z c, z c, z c, z z z z z z z z c c c, dc, z c, dc, z z 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 byte oriented skip operations decfsz incfsz f, d f, d decrement f, skip if 0 increment f, skip if 0 1(2) 1(2) 00 00 1011 1111 dfff dfff ffff ffff 1, 2 1, 2 bit-oriented file register operations bcf bsf f, b f, b bit clear f bit set f 1 1 01 01 00bb 01bb bfff bfff ffff ffff 2 2 bit-oriented skip operations btfsc btfss f, b f, b bit test f, skip if clear bit test f, skip if set 1 (2) 1 (2) 01 01 10bb 11bb bfff bfff ffff ffff 1, 2 1, 2 literal operations addlw andlw iorlw movlb movlp movlw sublw xorlw k k k k k k k k add literal and w and literal with w inclusive or literal with w move literal to bsr move literal to pclath move literal to w subtract w from literal exclusive or literal with w 1 1 1 1 1 1 1 1 11 11 11 00 11 11 11 11 1110 1001 1000 0000 0001 0000 1100 1010 kkkk kkkk kkkk 001k 1kkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk c, dc, z z z c, dc, z z note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle.
pic16(l)f1508/9 ds40001609b-page 310 ? 2011-2013 microchip technology inc. table 28-3: pic16(l)f1508/9 instruction set (continued) mnemonic, operands description cycles 14-bit opcode status affected notes msb lsb control operations bra brw call callw goto retfie retlw return k ? k ? k k k ? relative branch relative branch with w call subroutine call subroutine with w go to address return from interrupt return with literal in w return from subroutine 2 2 2 2 2 2 2 2 11 00 10 00 10 00 11 00 001k 0000 0kkk 0000 1kkk 0000 0100 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 0000 kkkk 1011 kkkk 1010 kkkk 1001 kkkk 1000 inherent operations clrwdt nop option reset sleep tris ? ? ? ? ? f clear watchdog timer no operation load option_reg register with w software device reset go into standby mode load tris register with w 1 1 1 1 1 1 00 00 00 00 00 00 0000 0000 0000 0000 0000 0000 0110 0000 0110 0000 0110 0110 0100 0000 0010 0001 0011 0fff to , pd to , pd c-compiler optimized addfsr moviw movwi n, k n mm k[n] n mm k[n] add literal k to fsrn move indirect fsrn to w with pre/post inc/dec modifier, mm move indfn to w, indexed indirect. move w to indirect fsrn with pre/post inc/dec modifier, mm move w to indfn, indexed indirect. 1 1 1 1 1 11 00 11 00 11 0001 0000 1111 0000 1111 0nkk 0001 0nkk 0001 1nkk kkkk 0nmm kkkk 1nmm kkkk z z 2, 3 2 2, 3 2 note 1: if the program counter (pc) is modified, or a conditional test is true, the instruction requires two cycles. the second cycle is executed as a nop . 2: if this instruction addresses an indf register and the msb of the corresponding fsr is set, this instruction will require one additional instruction cycle. 3: see table in the moviw and movwi instruction descriptions.
? 2011-2013 microchip technology inc. ds40001609b-page 311 pic16(l)f1508/9 28.2 instruction descriptions addfsr add literal to fsrn syntax: [ label ] addfsr fsrn, k operands: -32 ? k ? 31 n ? [ 0, 1] operation: fsr(n) + k ? fsr(n) status affected: none description: the signed 6-bit literal ?k? is added to the contents of the fsrnh:fsrnl register pair. fsrn is limited to the range 0000h - ffffh. moving beyond these bounds will cause the fsr to wrap-around. addlw add literal and w syntax: [ label ] addlw k operands: 0 ? k ? 255 operation: (w) + k ? (w) status affected: c, dc, z description: the contents of the w register are added to the 8-bit literal ?k? and the result is placed in the w register. addwf add w and f syntax: [ label ] addwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) + (f) ? (destination) status affected: c, dc, z description: add the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. addwfc add w and carry bit to f syntax: [ label ] addwfc f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (w) + (f) + (c) ? dest status affected: c, dc, z description: add w, the carry flag and data mem- ory location ?f?. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is placed in data memory location ?f?. andlw and literal with w syntax: [ label ] andlw k operands: 0 ? k ? 255 operation: (w) .and. (k) ? (w) status affected: z description: the contents of w register are and?ed with the 8-bit literal ?k?. the result is placed in the w register. andwf and w with f syntax: [ label ] andwf f,d operands: 0 ? f ? 127 d ??? 0 , 1 ? operation: (w) .and. (f) ? (destination) status affected: z description: and the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. asrf arithmetic right shift syntax: [ label ] asrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. the msb remains unchanged. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f c
pic16(l)f1508/9 ds40001609b-page 312 ? 2011-2013 microchip technology inc. bcf bit clear f syntax: [ label ] bcf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 0 ? (f) status affected: none description: bit ?b? in register ?f? is cleared. bra relative branch syntax: [ label ] bra label [ label ] bra $+k operands: -256 ? label - pc + 1 ? 255 -256 ? k ? 255 operation: (pc) + 1 + k ? pc status affected: none description: add the signed 9-bit literal ?k? to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + k. this instruction is a 2-cycle instruc- tion. this branch has a limited range. brw relative branch with w syntax: [ label ] brw operands: none operation: (pc) + (w) ? pc status affected: none description: add the contents of w (unsigned) to the pc. since the pc will have incre- mented to fetch the next instruction, the new address will be pc + 1 + (w). this instruction is a 2-cycle instruc- tion. bsf bit set f syntax: [ label ] bsf f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: 1 ? (f) status affected: none description: bit ?b? in register ?f? is set. btfsc bit test f, skip if clear syntax: [ label ] btfsc f,b operands: 0 ? f ? 127 0 ? b ? 7 operation: skip if (f) = 0 status affected: none description: if bit ?b? in register ?f? is ? 1 ?, the next instruction is executed. if bit ?b?, in register ?f?, is ? 0 ?, the next instruction is discarded, and a nop is executed instead, making this a 2-cycle instruction. btfss bit test f, skip if set syntax: [ label ] btfss f,b operands: 0 ? f ? 127 0 ? b < 7 operation: skip if (f) = 1 status affected: none description: if bit ?b? in register ?f? is ? 0 ?, the next instruction is executed. if bit ?b? is ? 1 ?, then the next instruction is discarded and a nop is executed instead, making this a 2-cycle instruction.
? 2011-2013 microchip technology inc. ds40001609b-page 313 pic16(l)f1508/9 call call subroutine syntax: [ label ] call k operands: 0 ? k ? 2047 operation: (pc)+ 1 ? tos, k ? pc<10:0>, (pclath<6:3>) ? pc<14:11> status affected: none description: call subroutine. first, return address (pc + 1) is pushed onto the stack. the 11-bit immediate address is loaded into pc bits <10:0>. the upper bits of the pc are loaded from pclath. call is a 2-cycle instruc- tion. callw subroutine call with w syntax: [ label ] callw operands: none operation: (pc) +1 ? tos, (w) ? pc<7:0>, (pclath<6:0>) ?? pc<14:8> status affected: none description: subroutine call with w. first, the return address (pc + 1) is pushed onto the return stack. then, the con- tents of w is loaded into pc<7:0>, and the contents of pclath into pc<14:8>. callw is a 2-cycle instruction. clrf clear f syntax: [ label ] clrf f operands: 0 ? f ? 127 operation: 00h ? (f) 1 ? z status affected: z description: the contents of register ?f? are cleared and the z bit is set. clrw clear w syntax: [ label ] clrw operands: none operation: 00h ? (w) 1 ? z status affected: z description: w register is cleared. zero bit (z) is set. clrwdt clear watchdog timer syntax: [ label ] clrwdt operands: none operation: 00h ? wdt 0 ? wdt prescaler, 1 ? to 1 ? pd status affected: to , pd description: clrwdt instruction resets the watch- dog timer. it also resets the prescaler of the wdt. status bits to and pd are set. comf complement f syntax: [ label ] comf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f ) ? (destination) status affected: z description: the contents of register ?f? are com- plemented. if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. decf decrement f syntax: [ label ] decf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination) status affected: z description: decrement register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?.
pic16(l)f1508/9 ds40001609b-page 314 ? 2011-2013 microchip technology inc. decfsz decrement f, skip if 0 syntax: [ label ] decfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) - 1 ? (destination); skip if result = 0 status affected: none description: the contents of register ?f? are decre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, then a nop is executed instead, making it a 2-cycle instruction. goto unconditional branch syntax: [ label ] goto k operands: 0 ? k ? 2047 operation: k ? pc<10:0> pclath<6:3> ? pc<14:11> status affected: none description: goto is an unconditional branch. the 11-bit immediate value is loaded into pc bits <10:0>. the upper bits of pc are loaded from pclath<4:3>. goto is a 2-cycle instruction. incf increment f syntax: [ label ] incf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination) status affected: z description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. incfsz increment f, skip if 0 syntax: [ label ] incfsz f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) + 1 ? (destination), skip if result = 0 status affected: none description: the contents of register ?f? are incre- mented. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. if the result is ? 1 ?, the next instruction is executed. if the result is ? 0 ?, a nop is executed instead, making it a 2-cycle instruction. iorlw inclusive or literal with w syntax: [ label ] iorlw k operands: 0 ? k ? 255 operation: (w) .or. k ? (w) status affected: z description: the contents of the w register are or?ed with the 8-bit literal ?k?. the result is placed in the w register. iorwf inclusive or w with f syntax: [ label ] iorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .or. (f) ? (destination) status affected: z description: inclusive or the w register with regis- ter ?f?. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?.
? 2011-2013 microchip technology inc. ds40001609b-page 315 pic16(l)f1508/9 lslf logical left shift syntax: [ label ] lslf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: (f<7>) ? c (f<6:0>) ? dest<7:1> 0 ? dest<0> status affected: c, z description: the contents of register ?f? are shifted one bit to the left through the carry flag. a ? 0 ? is shifted into the lsb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. lsrf logical right shift syntax: [ label ] lsrf f {,d} operands: 0 ? f ? 127 d ?? [0,1] operation: 0 ? dest<7> (f<7:1>) ? dest<6:0>, (f<0>) ? c, status affected: c, z description: the contents of register ?f? are shifted one bit to the right through the carry flag. a ? 0 ? is shifted into the msb. if ?d? is ? 0 ?, the result is placed in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. register f 0 c register f c 0 movf move f syntax: [ label ] movf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f) ? (dest) status affected: z description: the contents of register f is moved to a destination dependent upon the status of d. if d = 0 , destination is w register. if d = 1 , the destination is file register f itself. d = 1 is useful to test a file register since status flag z is affected. words: 1 cycles: 1 example: movf fsr, 0 after instruction w = value in fsr register z= 1
pic16(l)f1508/9 ds40001609b-page 316 ? 2011-2013 microchip technology inc. moviw move indfn to w syntax: [ label ] moviw ++fsrn [ label ] moviw --fsrn [ label ] moviw fsrn++ [ label ] moviw fsrn-- [ label ] moviw k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: indfn ? w effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) ? unchanged status affected: z mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. movlb move literal to bsr syntax: [ label ] movlb k operands: 0 ? k ? 31 operation: k ? bsr status affected: none description: the 5-bit literal ?k? is loaded into the bank select register (bsr). movlp move literal to pclath syntax: [ label ] movlp k operands: 0 ? k ? 127 operation: k ? pclath status affected: none description: the 7-bit literal ?k? is loaded into the pclath register. movlw move literal to w syntax: [ label ] movlw k operands: 0 ? k ? 255 operation: k ? (w) status affected: none description: the 8-bit literal ?k? is loaded into w reg- ister. the ?don?t cares? will assemble as ? 0 ?s. words: 1 cycles: 1 example: movlw 0x5a after instruction w = 0x5a movwf move w to f syntax: [ label ] movwf f operands: 0 ? f ? 127 operation: (w) ? (f) status affected: none description: move data from w register to register ?f?. words: 1 cycles: 1 example: movwf option_reg before instruction option_reg = 0xff w = 0x4f after instruction option_reg = 0x4f w = 0x4f
? 2011-2013 microchip technology inc. ds40001609b-page 317 pic16(l)f1508/9 movwi move w to indfn syntax: [ label ] movwi ++fsrn [ label ] movwi --fsrn [ label ] movwi fsrn++ [ label ] movwi fsrn-- [ label ] movwi k[fsrn] operands: n ? [ 0 , 1 ] mm ? [ 00 , 01 , 10 , 11 ] -32 ? k ? 31 operation: w ? indfn effective address is determined by ? fsr + 1 (preincrement) ? fsr - 1 (predecrement) ? fsr + k (relative offset) after the move, the fsr value will be either: ? fsr + 1 (all increments) ? fsr - 1 (all decrements) unchanged status affected: none mode syntax mm preincrement ++fsrn 00 predecrement --fsrn 01 postincrement fsrn++ 10 postdecrement fsrn-- 11 description: this instruction is used to move data between w and one of the indirect registers (indfn). before/after this move, the pointer (fsrn) is updated by pre/post incrementing/decrementing it. note: the indfn registers are not physical registers. any instruction that accesses an indfn register actually accesses the register at the address specified by the fsrn. fsrn is limited to the range 0000h - ffffh. incrementing/decrementing it beyond these bounds will cause it to wrap-around. the increment/decrement operation on fsrn will not affect any status bits. nop no operation syntax: [ label ] nop operands: none operation: no operation status affected: none description: no operation. words: 1 cycles: 1 example: nop option load option_reg register with w syntax: [ label ] option operands: none operation: (w) ? option_reg status affected: none description: move data from w register to option_reg register. reset software reset syntax: [ label ] reset operands: none operation: execute a device reset. resets the nri flag of the pcon register. status affected: none description: this instruct ion provides a way to execute a hardware reset by soft- ware.
pic16(l)f1508/9 ds40001609b-page 318 ? 2011-2013 microchip technology inc. retfie return from interrupt syntax: [ label ] retfie operands: none operation: tos ? pc, 1 ? gie status affected: none description: return from interrupt. stack is poped and top-of-stack (tos) is loaded in the pc. interrupts are enabled by setting global interrupt enable bit, gie (intcon<7>). this is a 2-cycle instruction. words: 1 cycles: 2 example: retfie after interrupt pc = tos gie = 1 retlw return with literal in w syntax: [ label ] retlw k operands: 0 ? k ? 255 operation: k ? (w); tos ? pc status affected: none description: the w register is loaded with the 8-bit literal ?k?. the program counter is loaded from the top of the stack (the return address). this is a 2-cycle instruction. words: 1 cycles: 2 example: table call table;w contains table ;offset value ? ;w now has table value ? ? addwf pc ;w = offset retlw k1 ;begin table retlw k2 ; ? ? ? retlw kn ; end of table before instruction w = 0x07 after instruction w = value of k8 return return from subroutine syntax: [ label ] return operands: none operation: tos ? pc status affected: none description: return from subroutine. the stack is poped and the top of the stack (tos) is loaded into the program counter. this is a 2-cycle instruction. rlf rotate left f through carry syntax: [ label ] rlf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the left through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f?. words: 1 cycles: 1 example: rlf reg1,0 before instruction reg1 = 1110 0110 c=0 after instruction reg1 = 1110 0110 w = 1100 1100 c=1 register f c
? 2011-2013 microchip technology inc. ds40001609b-page 319 pic16(l)f1508/9 rrf rotate right f through carry syntax: [ label ] rrf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: see description below status affected: c description: the contents of register ?f? are rotated one bit to the right through the carry flag. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed back in register ?f?. sleep enter sleep mode syntax: [ label ]sleep operands: none operation: 00h ? wdt, 0 ? wdt prescaler, 1 ? to , 0 ? pd status affected: to , pd description: the power-down status bit, pd is cleared. time-out status bit, to is set. watchdog timer and its pres- caler are cleared. the processor is put into sleep mode with the oscillator stopped. register f c sublw subtract w from literal syntax: [ label ]sublw k operands: 0 ?? k ?? 255 operation: k - (w) ??? w) status affected: c, dc, z description: the w register is subtracted (2?s com- plement method) from the 8-bit literal ?k?. the result is placed in the w regis- ter. subwf subtract w from f syntax: [ label ] subwf f,d operands: 0 ?? f ?? 127 d ? [ 0 , 1 ] operation: (f) - (w) ??? destination) status affected: c, dc, z description: subtract (2?s complement method) w register from register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in register ?f. subwfb subtract w from f with borrow syntax: subwfb f {,d} operands: 0 ? f ? 127 d ? [0,1] operation: (f) ? (w) ? (b ) ?? dest status affected: c, dc, z description: subtract w and the borrow flag (carry) from register ?f? (2?s comple- ment method). if ?d? is ? 0 ?, the result is stored in w. if ?d? is ? 1 ?, the result is stored back in register ?f?. c = 0 w ? k c = 1 w ? k dc = 0 w<3:0> ? k<3:0> dc = 1 w<3:0> ? k<3:0> c = 0 w ? f c = 1 w ? f dc = 0 w<3:0> ? f<3:0> dc = 1 w<3:0> ? f<3:0>
pic16(l)f1508/9 ds40001609b-page 320 ? 2011-2013 microchip technology inc. swapf swap nibbles in f syntax: [ label ] swapf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (f<3:0>) ? (destination<7:4>), (f<7:4>) ? (destination<3:0>) status affected: none description: the upper and lower nibbles of regis- ter ?f? are exchanged. if ?d? is ? 0 ?, the result is placed in the w register. if ?d? is ? 1 ?, the result is placed in register ?f?. tris load tris register with w syntax: [ label ] tris f operands: 5 ? f ? 7 operation: (w) ? tris register ?f? status affected: none description: move data from w register to tris register. when ?f? = 5, trisa is loaded. when ?f? = 6, trisb is loaded. when ?f? = 7, trisc is loaded. xorlw exclusive or literal with w syntax: [ label ]xorlw k operands: 0 ?? k ?? 255 operation: (w) .xor. k ??? w) status affected: z description: the contents of the w register are xor?ed with the 8-bit literal ?k?. the result is placed in the w register. xorwf exclusive or w with f syntax: [ label ] xorwf f,d operands: 0 ? f ? 127 d ? [ 0 , 1 ] operation: (w) .xor. (f) ??? destination) status affected: z description: exclusive or the contents of the w register with register ?f?. if ?d? is ? 0 ?, the result is stored in the w register. if ?d? is ? 1 ?, the result is stored back in regis- ter ?f?.
? 2011-2013 microchip technology inc. ds40001609b-page 321 pic16(l)f1508/9 29.0 electrical specifications 29.1 absolute maximum ratings (?) ambient temperature under bias................................................................................................. ..... -40c to +125c storage temperature ............................................................................................................ ............ -65c to +150c voltage on pins with respect to v ss on v dd pin pic16f1508/9 ........................................................................................................... -0.3v to +6.5v pic16lf1508/9 ......................................................................................................... -0.3v t o +4.0v on mclr pin .......................................................................................................................... . -0.3v to +9.0v on all other pins ............................................................................................................ -0.3v to (v dd + 0.3v) maximum current on v ss pin (1) -40c ? t a ? +85c .............................................................................................................. 170 ma -40c ? t a ? +125c .............................................................................................................. 70 ma on v dd pin (1) -40c ? t a ? +85c .............................................................................................................. 170 ma -40c ? t a ? +125c .............................................................................................................. 70 ma on any i/o pin ................................................................................................................ ..................... ? 25 ma clamp current, i k (v pin < 0 or v pin > v dd ) ................................................................................................... ? 20 ma ? notice: stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. exposure above maximum rating conditions for extended periods may affect device reliability. note 1: maximum current rating requires even load distribution across i/o pins. maximum current rating may be limited by the device package power dissipation characterizations, see tab le 2 9- 6 : ?thermal characteristics? to calculate device specifications.
pic16(l)f1508/9 ds40001609b-page 322 ? 2011-2013 microchip technology inc. 29.2 standard operating conditions the standard operating conditions for any device are defined as: operating voltage: v ddmin ?? v dd ?? v ddmax operating temperature: t a _ min ?? t a ?? t a _ max v dd ? operating supply voltage (1) pic16lf1508/9 v ddmin (fosc ? 16 mhz).......................................................................................................... +1.8v v ddmin (fosc ? 20 mhz).......................................................................................................... +2.5v v ddmax ............................................................................................................................... ..... +3.6v pic16f1508/9 v ddmin (fosc ? 16 mhz).......................................................................................................... +2.3v v ddmin (fosc ? 20 mhz).......................................................................................................... +2.5v v ddmax ............................................................................................................................... ..... +5.5v t a ? operating ambient temperature range industrial temperature t a _ min ............................................................................................................................... ....... -40c t a _ max ............................................................................................................................... ..... +85c extended temperature t a _ min ............................................................................................................................... ....... -40c t a _ max ............................................................................................................................... ... +125c note 1: see parameter d001 , ds characteristics: supply voltage.
? 2011-2013 microchip technology inc. ds40001609b-page 323 pic16(l)f1508/9 figure 29-1: voltage frequency graph, -40c ? t a ?? +125c, pic16f1508/9 only figure 29-2: voltage frequency graph, -40c ? t a ?? +125c, pic16lf1508/9 only note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 29-7 for each oscillator mode?s supported frequencies. 2.3 0 2.5 frequency (mhz) v dd (v) 420 10 16 5.5 note 1: the shaded region indicates the permissible combinations of voltage and frequency. 2: refer to table 29-7 for each oscillator mode?s supported frequencies. 1.8 0 2.5 frequency (mhz) v dd (v) 420 10 16 3.6
pic16(l)f1508/9 ds40001609b-page 324 ? 2011-2013 microchip technology inc. 29.3 dc characteristics table 29-1: supply voltage pic16lf1508/9 standard operating conditions (unless otherwise stated) pic16f1508/9 param. no. sym. characteristic min. typ? max. units conditions d001 v dd supply voltage v ddmin 1.8 2.5 ? ? v ddmax 3.6 3.6 v v f osc ? 16 mhz f osc ? 20 mhz d001 2.3 2.5 ? ? 5.5 5.5 v v f osc ? 16 mhz f osc ? 20 mhz d002* v dr ram data retention voltage (1) 1.5 ? ? v device in sleep mode d002* 1.7 ? ? v device in sleep mode d002a* v por power-on reset release voltage (2) ?1.6? v d002a* ? 1.6 ? v d002b* v porr * power-on reset rearm voltage (2) ?0.8? v d002b* ? 1.5 ? v d003 v fvr fixed voltage reference voltage ? 1.024 ? v -40c ? t a ? +85c d003a v adfvr fvr gain voltage accuracy for adc -4 ? +4 % 1x v fvr , adfvr = 01 , v dd ?? 2.5v 2x v fvr , adfvr = 10 , v dd ?? 2.5v 4x v fvr , adfvr = 11 , v dd ?? 4.75v d003b v cdafvr fvr gain voltage accuracy for comparator -4 ? +4 % 1x v fvr , cdafvr = 01 , v dd ?? 2.5v 2x v fvr , cdafvr = 10 , v dd ?? 2.5v 4x v fvr , cdafvr = 11 , v dd ?? 4.75v d004* s vdd v dd rise rate (2) 0.05 ? ? v/ms ensures that the power-on reset signal is released properly. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: this is the limit to which v dd can be lowered in sleep mode without losing ram data. 2: see figure 29-3 , por and por rearm with slow rising v dd .
? 2011-2013 microchip technology inc. ds40001609b-page 325 pic16(l)f1508/9 figure 29-3: por and por rearm with slow rising v dd v dd v por v porr v ss v ss npor (1) t por (3) por rearm note 1: when npor is low, the device is held in reset. 2: t por 1 ? s typical. 3: t vlow 2.7 ? s typical. t vlow (2) s vdd
pic16(l)f1508/9 ds40001609b-page 326 ? 2011-2013 microchip technology inc. table 29-2: supply current (i dd ) (1,2) pic16lf1508/9 standard operating conditions (unless otherwise stated) pic16f1508/9 param. no. device characteristics min. typ? max. units conditions v dd note d010 ? 8 20 ? a1.8f osc = 32 khz, lp oscillator, -40c ? t a ? +85c ?10 25 ? a3.0 d010 ? 15 31 ? a 2.3 f osc = 32 khz, lp oscillator, -40c ? t a ? +85c ? 17 33 ? a 3.0 ? 21 39 ? a 5.0 d011 ? 60 100 ? a1.8f osc = 1 mhz, xt oscillator ? 100 180 ? a3.0 d011 ? 100 180 ? a 2.3 f osc = 1 mhz, xt oscillator ? 130 220 ? a 3.0 ? 170 280 ? a 5.0 d012 ? 140 240 ? a1.8f osc = 4 mhz, xt oscillator ? 250 360 ? a3.0 d012 ? 210 320 ? a 2.3 f osc = 4 mhz, xt oscillator ? 280 410 ? a 3.0 ? 340 500 ? a 5.0 d013 ? 30 65 ? a1.8f osc = 1 mhz, external clock (ecm), medium-power mode ?55100 ? a3.0 d013 ? 65 110 ? a 2.3 f osc = 1 mhz, external clock (ecm), medium-power mode ? 85 140 ? a 3.0 ? 115 190 ? a 5.0 d014 ? 115 190 ? a1.8f osc = 4 mhz, external clock (ecm), medium-power mode ? 210 310 ? a3.0 d014 ? 180 270 ? a 2.3 f osc = 4 mhz, external clock (ecm), medium-power mode ? 240 365 ? a 3.0 ? 295 460 ? a 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for extrc oscillator configurations, current through r ext is not included. the current through the resis- tor can be extended by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2011-2013 microchip technology inc. ds40001609b-page 327 pic16(l)f1508/9 d015 ? 3.2 12 ? a1.8f osc = 31 khz, lfintosc, -40c ? t a ? +85c ?5.4 20 ? a3.0 d015 ? 13 28 ? a 2.3 f osc = 31 khz, lfintosc, -40c ? t a ? +85c ? 15 30 ? a 3.0 ? 17 36 ? a 5.0 d016 ? 215 360 ? a1.8f osc = 500 khz, hfintosc ? 275 480 ? a3.0 d016 ? 270 450 ? a 2.3 f osc = 500 khz, hfintosc ? 300 500 ? a 3.0 ? 350 620 ? a 5.0 d017* ? 410 660 ? a1.8f osc = 8 mhz, hfintosc ? 630 970 ? a3.0 d017* ? 530 750 ? a 2.3 f osc = 8 mhz, hfintosc ? 660 1100 ? a 3.0 ? 730 1200 ? a 5.0 d018 ? 600 940 ? a1.8f osc = 16 mhz, hfintosc ? 970 1400 ? a3.0 d018 ? 780 1200 ? a 2.3 f osc = 16 mhz, hfintosc ? 1000 1550 ? a 3.0 ? 1090 1700 ? a 5.0 d019a ? 1030 1500 ? a3.0f osc = 20 mhz, external clock (ech), high-power mode d019a ? 1060 1600 ? a 3.0 f osc = 20 mhz, external clock (ech), high-power mode ? 1220 1800 ? a 5.0 table 29-2: supply current (i dd ) (1,2) (continued) pic16lf1508/9 standard operating conditions (unless otherwise stated) pic16f1508/9 param. no. device characteristics min. typ? max. units conditions v dd note * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for extrc oscillator configurations, current through r ext is not included. the current through the resis- tor can be extended by the formula ir = v dd /2r ext (ma) with r ext in k ? .
pic16(l)f1508/9 ds40001609b-page 328 ? 2011-2013 microchip technology inc. d019b ? 6 16 ? a1.8f osc = 32 khz, external clock (ecl), low-power mode ?8 22 ? a3.0 d019b ? 13 28 ? a 2.3 f osc = 32 khz, external clock (ecl), low-power mode ? 15 31 ? a 3.0 ? 16 36 ? a 5.0 d019c ? 19 35 ? a1.8f osc = 500 khz, external clock (ecl), low-power mode ?32 55 ? a3.0 d019c ? 31 52 ? a 2.3 f osc = 500 khz, external clock (ecl), low-power mode ? 38 65 ? a 3.0 ? 44 74 ? a 5.0 d020 ? 140 210 ? a1.8f osc = 4 mhz, extrc ( note 3 ) ? 250 330 ? a3.0 d020 ? 210 290 ? a 2.3 f osc = 4 mhz, extrc ( note 3 ) ? 280 380 ? a 3.0 ? 350 470 ? a 5.0 d021 ? 1135 1700 ? a3.0f osc = 20 mhz, hs oscillator d021 ? 1170 1800 ? a 3.0 f osc = 20 mhz, hs oscillator ? 1555 2300 ? a 5.0 table 29-2: supply current (i dd ) (1,2) (continued) pic16lf1508/9 standard operating conditions (unless otherwise stated) pic16f1508/9 param. no. device characteristics min. typ? max. units conditions v dd note * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the test conditions for all i dd measurements in active operation mode are: osc1 = external square wave, from rail-to-rail; all i/o pins tri-stated, pulled to v ss ; mclr = v dd ; wdt disabled. 2: the supply current is mainly a function of the operating voltage and frequency. other factors, such as i/o pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. 3: for extrc oscillator configurations, current through r ext is not included. the current through the resis- tor can be extended by the formula ir = v dd /2r ext (ma) with r ext in k ? .
? 2011-2013 microchip technology inc. ds40001609b-page 329 pic16(l)f1508/9 table 29-3: power-down currents (i pd ) (1,2) pic16lf1508/9 operating conditions: (unless otherwise stated) low-power sleep mode pic16f1508/9 low-power sleep mode, vregpm = 1 param. no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note d022 base i pd ? 0.020 1.0 8.0 ? a 1.8 wdt, bor, fvr and sosc disabled, all peripherals inactive ? 0.025 2.0 9.0 ? a3.0 d022 base i pd ? 0.25 3.0 10 ? a 2.3 wdt, bor, fvr and sosc disabled, all peripherals inactive, low-power sleep mode ? 0.30 4.0 12 ? a 3.0 ? 0.40 6.0 15 ? a 5.0 d022a base i pd ? 9.8 16 18 ? a 2.3 wdt, bor, fvr and sosc disabled, all peripherals inactive, normal-power sleep mode, vregpm = 0 ? 10.3 18 20 ? a 3.0 ? 11.5 21 26 ? a 5.0 d023 ? 0.26 2.0 9.0 ? a 1.8 wdt current ? 0.44 3.0 10 ? a3.0 d023 ? 0.43 6.0 15 ? a 2.3 wdt current ? 0.53 7.0 20 ? a 3.0 ? 0.64 8.0 22 ? a 5.0 d023a ? 15 28 30 ? a 1.8 fvr current ?18 30 33 ? a3.0 d023a ? 18 33 35 ? a 2.3 fvr current ? 19 35 37 ? a 3.0 ? 20 37 39 ? a 5.0 d024 ? 6.0 17 20 ? a 3.0 bor current d024 ? 7.0 17 30 ? a 3.0 bor current ? 8.0 20 40 ? a 5.0 d24a ? 0.1 4.0 10 ? a 3.0 lpbor current d24a ? 0.35 5.0 14 ? a 3.0 lpbor current ? 0.45 8.0 17 ? a 5.0 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral ? current can be determined by subtracting the base i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v ss . 3: adc clock source is frc.
pic16(l)f1508/9 ds40001609b-page 330 ? 2011-2013 microchip technology inc. d025 ? 0.7 4.0 9.0 ? a 1.8 sosc current ?2.38.0 12 ? a3.0 d025 ? 1.0 6.0 11 ? a 2.3 sosc current ? 2.4 8.5 20 ? a 3.0 ? 6.9 20 25 ? a 5.0 d026 ? 0.11 1.5 9.0 ? a 1.8 adc current (note 3) , no conversion in progress ? 0.12 2.7 10 ? a3.0 d026 ? 0.30 4.0 11 ? a 2.3 adc current (note 3) , no conversion in progress ? 0.35 5.0 13 ? a 3.0 ? 0.45 8.0 16 ? a 5.0 d026a* ? 250 ? ? ? a 1.8 adc current (note 3) , conversion in progress ?250 ? ? ? a3.0 d026a* ? 280 ? ? ? a 2.3 adc current (note 3) , conversion in progress ? 280 ? ? ? a 3.0 ? 280 ? ? ? a 5.0 d027 ? 7 22 25 ? a 1.8 comparator, cxsp = 0 ? 8 23 27 ? a3.0 d027 ? 17 35 37 ? a 2.3 comparator, cxsp = 0 ? 18 37 38 ? a 3.0 ? 19 38 40 ? a 5.0 table 29-3: power-down currents (i pd ) (1,2) (continued) pic16lf1508/9 operating conditions: (unless otherwise stated) low-power sleep mode pic16f1508/9 low-power sleep mode, vregpm = 1 param. no. device characteristics min. typ? max. +85c max. +125c units conditions v dd note * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the peripheral ? current can be determined by subtracting the base i pd current from this limit. max. values should be used when calculating total current consumption. 2: the power-down current in sleep mode does not depend on the oscillator type. power-down current is measured with the part in sleep mode, with all i/o pins in high-impedance state and tied to v ss . 3: adc clock source is frc.
? 2011-2013 microchip technology inc. ds40001609b-page 331 pic16(l)f1508/9 table 29-4: i/o ports standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions v il input low voltage i/o port: d030 with ttl buffer ? ? 0.8 v 4.5v ? v dd ? 5.5v d030a ? ? 0.15 v dd v1.8v ? v dd ? 4.5v d031 with schmitt trigger buffer ? ? 0.2 v dd v2.0v ? v dd ? 5.5v with i 2 c? levels ? ? 0.3 v dd v with smbus levels ? ? 0.8 v 2.7v ? v dd ? 5.5v d032 mclr , osc1 (extrc mode) ? ? 0.2 v dd v (note 1) d033 osc1 (hs mode) ? ? 0.3 v dd v v ih input high voltage i/o port: d040 with ttl buffer 2.0 ? ? v 4.5v ? v dd ?? 5.5v d040a 0.25 v dd + 0.8 ??v1.8v ? v dd ? 4.5v d041 with schmitt trigger buffer 0.8 v dd ??v2.0v ? v dd ? 5.5v with i 2 c? levels 0.7 v dd ??v with smbus levels 2.1 ? ? v 2.7v ? v dd ? 5.5v d042 mclr 0.8 v dd ??v d043a osc1 (hs mode) 0.7 v dd ??v d043b osc1 (extrc mode) 0.9 v dd ??vv dd ? 2.0v (note 1) i il input leakage current (2) d060 i/o ports ? 5 125 na v ss ? v pin ? v dd , pin at high-impedance, 85c ? 5 1000 na v ss ? v pin ? v dd , pin at high-impedance, 125c d061 mclr (3) ? 50 200nav ss ? v pin ? v dd , pin at high-impedance, 85c i pur weak pull-up current d070* 25 100 200 ? av dd = 3.3v, v pin = v ss 25 140 300 ? av dd = 5.0v, v pin = v ss v ol output low voltage (4) d080 i/o ports ??0.6v i ol = 8 ma, v dd = 5v i ol = 6 ma, v dd = 3.3v i ol = 1.8 ma, v dd = 1.8v v oh output high voltage (4) d090 i/o ports v dd - 0.7 ? ? v i oh = 3.5 ma, v dd = 5v i oh = 3 ma, v dd = 3.3v i oh = 1 ma, v dd = 1.8v d101* cosc2 capacitive loading specifications on output pins osc2 pin ? ? 15 pf in xt, hs, lp modes when external clock is used to drive osc1 d101a* cio all i/o pins ? ? 50 pf * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: in extrc oscillator configuration, the osc1/clkin pin is a schmitt trigger input. it is not recommended to use an external clock in extrc mode. 2: negative current is defined as current sourced by the pin. 3: the leakage current on the mclr pin is strongly dependent on the applied voltage level. the specified levels represent normal operating conditions. higher leakage current may be measured at different input voltages. 4: excluding osc2 in clkout mode.
pic16(l)f1508/9 ds40001609b-page 332 ? 2011-2013 microchip technology inc. table 29-5: memory prog ramming specifications standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions program memory programming specifications d110 v ihh voltage on mclr /v pp pin 8.0 ? 9.0 v (note 2) d111 i ddp supply current during programming ??10ma d112 v be v dd for bulk erase 2.7 ? v ddmax v d113 v pew v dd for write or row erase v ddmin ?v ddmax v d114 i pppgm current on mclr /v pp during erase/write ?1.0?ma d115 i ddpgm current on v dd during erase/write ?5.0? ma program flash memory d121 e p cell endurance 10k ? ? e/w -40 ? c ? t a ? +85 ? c (note 1) d122 v prw v dd for read/write v ddmin ?v ddmax v d123 t iw self-timed write cycle time ? 2 2.5 ms d124 t retd characteristic retention ? 40 ? year provided no other specifications are violated d125 e hefc high-endurance flash cell 100k ? ? e/w 0c to +60c, lower byte last 128 addresses ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: self-write and block erase. 2: required only if single-supply programming is disabled.
? 2011-2013 microchip technology inc. ds40001609b-page 333 pic16(l)f1508/9 table 29-6: thermal characteristics standard operating conditions (unless otherwise stated) param. no. sym. characteristic typ. units conditions th01 ? ja thermal resistance junction to ambient 62.2 ? c/w 20-pin dip package 77.7 ? c/w 20-pin soic package 87.3 ? c/w 20-pin ssop package 43 ? c/w 20-pin qfn 4x4mm package th02 ? jc thermal resistance junction to case 27.5 ? c/w 20-pin dip package 23.1 ? c/w 20-pin soic package 31.1 ? c/w 20-pin ssop package 5.3 ? c/w 20-pin qfn 4x4mm package th03 t jmax maximum junction temperature 150 ? c th04 pd power dissipation ? w pd = p internal + p i / o th05 p internal internal power dissipation ? w p internal = i dd x v dd (1) th06 p i / o i/o power dissipation ? w p i / o = ? (i ol * v ol ) + ? (i oh * (v dd - v oh )) th07 p der derated power ? w p der = pd max (t j - t a )/ ? ja (2) note 1: i dd is current to run the chip alone without driving any load on the output pins. 2: t a = ambient temperature; t j = junction temperature
pic16(l)f1508/9 ds40001609b-page 334 ? 2011-2013 microchip technology inc. 29.4 ac characteristics timing parameter symbology has been created with one of the following formats: figure 29-4: load conditions figure 29-5: clock timing 1. tpps2pps 2. tpps t f frequency t time lowercase letters (pp) and their meanings: pp cc ccp1 osc clkin ck clkout rd rd cs cs rw rd or wr di sdix sc sckx do sdo ss ss dt data in t0 t0cki io i/o port t1 t1cki mc mclr wr wr uppercase letters and their meanings: s ffall pperiod hhigh rrise i invalid (high-impedance) v valid l low z high-impedance v ss c l legend: c l = 50 pf for all pins load condition pin clkin clkout q4 q1 q2 q3 q4 q1 os02 os03 (clkout mode) note 1: see table 29-9 . os11 os12
? 2011-2013 microchip technology inc. ds40001609b-page 335 pic16(l)f1508/9 table 29-7: clock oscillator timing requirements standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions os01 f osc external clkin frequency (1) dc ? 0.5 mhz external clock (ecl) dc ? 4 mhz external clock (ecm) dc ? 20 mhz external clock (ech) oscillator frequency (1) ? 32.768 ? khz lp oscillator 0.1 ? 4 mhz xt oscillator 1 ? 4 mhz hs oscillator 1 ? 20 mhz hs oscillator, v dd > 2.7v dc ? 4 mhz extrc, v dd > 2.0v os02 t osc external clkin period (1) 27 ? ? s lp oscillator 250 ? ? ns xt oscillator 50 ? ? ns hs oscillator 50 ? ? ns external clock (ec) oscillator period (1) ? 30.5 ? s lp oscillator 250 ? 10,000 ns xt oscillator 50 ? 1,000 ns hs oscillator 250 ? ? ns extrc os03 t cy instruction cycle time (1) 200 t cy dc ns t cy = 4/f osc os04* tosh, tosl external clkin high external clkin low 2 ? ? s lp oscillator 100 ? ? ns xt oscillator 20 ? ? ns hs oscillator os05* tosr, tosf external clkin rise external clkin fall 0 ? ? ns lp oscillator 0 ? ? ns xt oscillator 0 ? ? ns hs oscillator * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: instruction cycle period (t cy ) equals four times the input oscillator time base period. all specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current con- sumption. all devices are tested to operate at ?min? values with an external clock applied to clkin pin. when an external clock input is used, the ?max? cycle time limit is ?dc? (no clock) for all devices.
pic16(l)f1508/9 ds40001609b-page 336 ? 2011-2013 microchip technology inc. table 29-8: oscillator parameters figure 29-6: hfintosc frequency accuracy over v dd and temperature standard operating conditions (unless otherwise stated) param. no. sym. characteristic freq. tolerance min. typ? max. units conditions os08 hf osc internal calibrated hfintosc frequency (1) 2% ? 16.0 ? mhz v dd = 3.0v, t a = 25c, (note 2) os09 lf osc internal lfintosc frequency ? ? 31 ? khz (note 3) os10* t iosc st hfintosc wake-up from sleep start-up time ??515 ? s os10a* t lfosc st lfintosc wake-up from sleep start-up time ? ? 0.5 ? ms -40c ? t a ? +125c * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: to ensure these oscillator frequency tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended. 2: see figure 29-6 : ?hfintosc frequency accuracy over device v dd and temperature?, figure 30-73 : ?hfintosc accuracy over temperature, v dd = 1.8v, pic16lf1508/9 only?, and figure 30-74 : ?hfintosc accuracy over temperature, 2.3v ? v dd ?? 5.5v?. 3: see figure 30-71 : ?lfintosc frequency over v dd and temperature, pic16lf1508/9 only?, and figure 30-72 : ? lfintosc frequency over v dd and temperature, pic16f1508/9?. 125 25 2.0 0 60 85 v dd (v) 4.0 5.0 4.5 temperature ( c ) 2.5 3.0 3.5 5.5 1.8 -40 12% 12% 4.5% -4.5% to +7% 2.3 note: see figure 30-73 : ?hfintosc accuracy over temperature, v dd = 1.8v, pic16lf1508/9 only?, and figure 30-74 : ?hfintosc accuracy over temperature, 2.3v ?? v dd ? 5.5v?.
? 2011-2013 microchip technology inc. ds40001609b-page 337 pic16(l)f1508/9 figure 29-7: clkout and i/o timing table 29-9: clkout and i/o timing parameters standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions os11 tosh2ckl f osc ? to clkout ? (1) ? ? 70 ns 3.3v ? v dd ?? 5.0v os12 tosh2ckh f osc ? to clkout ? (1) ? ? 72 ns 3.3v ? v dd ?? 5.0v os13 tckl2iov clkout ? to port out valid (1) ? ? 20 ns os14 tiov2ckh port input valid before clkout ? (1) t osc + 200 ns ? ? ns os15 tosh2iov fosc ? (q1 cycle) to port out valid ? 50 70* ns 3.3v ? v dd ?? 5.0v os16 tosh2ioi fosc ? (q2 cycle) to port input invalid (i/o in setup time) 50 ? ? ns 3.3v ? v dd ?? 5.0v os17 tiov2osh port input valid to fosc ?? (q2 cycle) (i/o in setup time) 20 ? ? ns os18* tior port output rise time ? ? 40 15 72 32 ns v dd = 1.8v 3.3v ? v dd ?? 5.0v os19* tiof port output fall time ? ? 28 15 55 30 ns v dd = 1.8v 3.3v ? v dd ?? 5.0v os20* tinp int pin input high or low time 25 ? ? ns os21* tioc interrupt-on-change new input level time 25 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25 ? c unless otherwise stated. note 1: measurements are taken in extrc mode where clkout output is 4 x t osc . f osc clkout i/o pin (input) i/o pin (output) q4 q1 q2 q3 os11 os19 os13 os15 os18, os19 os20 os21 os17 os16 os14 os12 os18 old value new value write fetch read execute cycle
pic16(l)f1508/9 ds40001609b-page 338 ? 2011-2013 microchip technology inc. figure 29-8: reset, watchdog timer, os cillator start-up timer and power-up timer timing figure 29-9: brown-out rese t timing and characteristics v dd mclr internal por pwrt time-out osc start-up time internal reset(1) watchdog timer 33 32 30 31 34 i/o pins 34 note 1: asserted low. reset(1) v bor v dd (device in brown-out reset) (device not in brown-out reset) 33 (1) note 1: 64 ms delay only if pwrte bit in the configuration words is programmed to ? 0 ?. 2 ms delay if pwrte = 0 . reset (due to bor) v bor and v hyst 37
? 2011-2013 microchip technology inc. ds40001609b-page 339 pic16(l)f1508/9 table 29-10: reset, watchdog timer, oscill ator start-up timer, power-up timer and brown-out reset parameters standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions 30 t mc lmclr pulse width (low) 2 ? ? ? s 31 t wdtlp low-power watchdog timer time-out period 10 16 27 ms v dd = 3.3v-5v, 1:16 prescaler used 32 t ost oscillator start-up timer period (1) ? 1024 ? t osc 33* t pwrt power-up timer period, pwrte = 0 40 65 140 ms 34* t ioz i/o high-impedance from mclr low or watchdog timer reset ??2.0 ? s 35 v bor brown-out reset voltage (2) 2.55 2.35 1.80 2.70 2.45 1.90 2.85 2.58 2.05 v v v borv = 0 borv = 1 (pic16f1508/9) borv = 1 (pic16lf1508/9) 36* v hyst brown-out reset hysteresis 0 25 60 mv -40c ? t a ? +85c 37* t bordc brown-out reset dc response time 1 16 35 ? sv dd ? v bor 38 v lpbor low-power brown-out reset voltage 1.8 2.1 2.5 v lpbor = 1 * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: by design, the oscillator start-up timer (ost) counts the first 1024 cycles, independent of frequency. 2: to ensure these voltage tolerances, v dd and v ss must be capacitively decoupled as close to the device as possible. 0.1 ? f and 0.01 ? f values in parallel are recommended.
pic16(l)f1508/9 ds40001609b-page 340 ? 2011-2013 microchip technology inc. figure 29-10: timer0 and time r1 external clock timings table 29-11: timer0 and timer1 external clock requirements standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions 40* t t 0h t0cki high pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 41* t t 0l t0cki low pulse width no prescaler 0.5 t cy + 20 ? ? ns with prescaler 10 ? ? ns 42* t t 0p t0cki period greater of: 20 or t cy + 40 n ? ? ns n = prescale value 45* t t 1h t1cki high time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 46* t t 1l t1cki low time synchronous, no prescaler 0.5 t cy + 20 ? ? ns synchronous, with prescaler 15 ? ? ns asynchronous 30 ? ? ns 47* t t 1p t1cki input period synchronous greater of: 30 or t cy + 40 n ? ? ns n = prescale value asynchronous 60 ? ? ns 48 f t 1 secondary oscillator input frequency range (oscillator enabled by setting bit t1oscen) 32.4 32.768 33.1 khz 49* tckez tmr 1 delay from external clock edge to timer increment 2 t osc ?7 t osc ? timers in sync mode * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise st ated. these parameters are for design guidance only and are not tested. t0cki t1cki 40 41 42 45 46 47 49 tmr0 or tmr1
? 2011-2013 microchip technology inc. ds40001609b-page 341 pic16(l)f1508/9 figure 29-11: clc pr opagation timing table 29-12: config uration logic cell (clc) characteristics standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions clc01* t clcin clc input time ? 7 ? ns clc02* t clc clc module input to output progagation time ? ? 24 12 ? ? ns ns v dd = 1.8v v dd > 3.6v clc03* t clcout clc output time rise time ? os18 ? ? (note 1) fall time ? os19 ? ? (note 1) clc04* f clcmax clc maximum switching frequency ? 45 ? mhz * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: see table 29-9 for os18 and os19 rise and fall times. lcx_in[n] (1) clc output time clc input time lcx_out (1) clcx clcxinn clc module clc01 clc02 clc03 lcx_in[n] (1) clc output time clc input time lcx_out (1) clcx clcxinn clc module rev. 10-000031a_a3 note 1: see figure 24-1 , clc simplified block diagram.
pic16(l)f1508/9 ds40001609b-page 342 ? 2011-2013 microchip technology inc. table 29-13: analog-to-digital converter (adc) characteristics (1,2,3,4) operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c param. no. sym. characteristic min. typ? max. units conditions ad01 n r resolution ? ? 10 bit ad02 e il integral error ? 1 1.7 lsb v ref = 3.0v ad03 e dl differential error ? 1 1 lsb no missing codes v ref = 3.0v ad04 e off offset error ? 1 2.5 lsb v ref = 3.0v ad05 e gn gain error ? 1 2.0 lsb v ref = 3.0v ad06 v ref reference voltage 1.8 ? v dd vv ref = (v ref + minus v ref -) ad07 v ain full-scale range v ss ?v ref v ad08 z ain recommended impedance of analog voltage source ?? 10k ? can go higher if external 0.01 ? f capacitor is present on input pin. * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: total absolute error includes integral, differential, offset and gain errors. 2: the adc conversion result never decreases with an increase in the input voltage and has no missing codes. 3: adc v ref is from external v ref or the v dd pin, whichever is selected as reference input. 4: see section 30.0 ?dc and ac characteristics graphs and charts? for operating characterization.
? 2011-2013 microchip technology inc. ds40001609b-page 343 pic16(l)f1508/9 figure 29-12: adc conversi on timing (adc clock f osc -based) figure 29-13: adc conversion timing (adc clock from frc) ad131 ad130 bsf adcon0, go q4 adc_clk adc data adres adif go sample old_data sampling stopped done new_data 987 3210 1 t cy 6 ad133 1 t cy ad132 ad132 ad131 ad130 bsf adcon0, go q4 adc_clk adc data adres adif go sample old_data sampling stopped done new_data 9 7 3210 note 1: if the adc clock source is selected as frc, a time of t cy is added before the adc clock starts. this allows the sleep instruction to be executed. ad133 6 8 1 t cy 1 t cy
pic16(l)f1508/9 ds40001609b-page 344 ? 2011-2013 microchip technology inc. table 29-14: adc conversion requirements standard operating conditions (unless otherwise stated) param. no. sym. characteristic min. typ? max. units conditions ad130* t ad adc clock period (t adc )1.0?6.0 ? sf osc -based adc internal frc oscillator period (t frc )1.0 2.0 6.0 ? s adcs<2:0> = x11 (adc frc mode) ad131 t cnv conversion time (not including acquisition time) (1) ?11?t ad set go/done bit to conversion complete ad132* t acq acquisition time ? 5.0 ? ? s ad133* t hcd holding capacitor disconnect time ? ? 1/2 t ad 1/2 t ad + 1t cy ? ? f osc -based adcs<2:0> = x11 (adc frc mode) * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested. note 1: the adres register may be read on the following t cy cycle.
? 2011-2013 microchip technology inc. ds40001609b-page 345 pic16(l)f1508/9 table 29-15: comparator specifications (1) table 29-16: digital-to-analog co nverter (dac) specifications (1) operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c param. no. sym. characteristics min. typ. max. units comments cm01 v ioff input offset voltage ? 7.5 60 mv cxsp = 1 , v icm = v dd /2 cm02 v icm input common mode voltage 0 ? vdd v cm03 c mrr common mode rejection ration ? 50 ? db cm04a t resp (2) response time rising edge ? 400 800 ns cxsp = 1 cm04b response time falling edge ? 200 400 ns cxsp = 1 cm04c response time rising edge ? 1200 ? ns cxsp = 0 cm04d response time falling edge ? 550 ? ns cxsp = 0 cm05* t mc 2 ov comparator mode change to output valid ??10 ? s cm06 c hyster comparator hysteresis ? 25 ? mv cxhys = 1 , cxsp = 1 * these parameters are characterized but not tested. note 1: see section 30.0 ?dc and ac characteristics graphs and charts? for operating characterization. 2: response time measured with one comparator input at v dd /2, while the other input transitions from v ss to v dd . operating conditions (unless otherwise stated) v dd = 3.0v, t a = 25c param. no. sym. characteristics min. typ. max. units comments dac01* c lsb step size ? v dd /32 ? v dac02* c acc absolute accuracy ? ? ? 1/2 lsb dac03* c r unit resistor value (r) ? 5k ? ? dac04* c st settling time (2) ??10 ? s * these parameters are characterized but not tested. note 1: see section 30.0 ?dc and ac characteristics graphs and charts? for operating characterization. 2: settling time measured while dacr<4:0> transitions from ? 0000 ? to ? 1111 ?.
pic16(l)f1508/9 ds40001609b-page 346 ? 2011-2013 microchip technology inc. figure 29-14: usart synchronous transmission (master/slave) timing table 29-17: usart synchronous tran smission requirements figure 29-15: usart synchrono us receive (master/slave) timing table 29-18: usart synchronous rece ive requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions us120 t ck h2 dt v sync xmit (m aster and s lave ) clock high to data-out valid ?80ns3.0v ? v dd ? 5.5v ? 100 ns 1.8v ? v dd ? 5.5v us121 t ckrf clock out rise time and fall time (master mode) ?45ns3.0v ? v dd ? 5.5v ?50ns1.8v ? v dd ? 5.5v us122 t dtrf data-out rise time and fall time ? 45 ns 3.0v ? v dd ? 5.5v ?50ns1.8v ? v dd ? 5.5v standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions us125 t dt v2 ckl sync rcv (m aster and s lave ) data-hold before ck ? (dt hold time) 10 ? ns us126 t ck l2 dtl data-hold after ck ? (dt hold time) 15 ? ns note: refer to figure 29-4 for load conditions. us121 us121 us120 us122 ck dt note: refer to figure 29-4 for load conditions. us125 us126 ck dt
? 2011-2013 microchip technology inc. ds40001609b-page 347 pic16(l)f1508/9 figure 29-16: spi master mode timing (cke = 0 , smp = 0 ) figure 29-17: spi master mode timing (cke = 1 , smp = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp81 sp71 sp72 sp73 sp74 sp75, sp76 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in lsb in bit 6 - - - -1 note: refer to figure 29-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp81 sp71 sp72 sp74 sp75, sp76 sp78 sp80 msb sp79 sp73 msb in bit 6 - - - - - -1 lsb in bit 6 - - - -1 lsb note: refer to figure 29-4 for load conditions.
pic16(l)f1508/9 ds40001609b-page 348 ? 2011-2013 microchip technology inc. figure 29-18: spi slav e mode timing (cke = 0 ) figure 29-19: spi slav e mode timing (cke = 1 ) ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp73 sp74 sp75, sp76 sp77 sp78 sp79 sp80 sp79 sp78 msb lsb bit 6 - - - - - -1 msb in bit 6 - - - -1 lsb in sp83 note: refer to figure 29-4 for load conditions. ss sck (ckp = 0 ) sck (ckp = 1 ) sdo sdi sp70 sp71 sp72 sp82 sp74 sp75, sp76 msb bit 6 - - - - - -1 lsb sp77 msb in bit 6 - - - -1 lsb in sp80 sp83 note: refer to figure 29-4 for load conditions.
? 2011-2013 microchip technology inc. ds40001609b-page 349 pic16(l)f1508/9 table 29-19: spi mode requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. typ? max. units conditions sp70* t ss l2 sc h, t ss l2 sc l ss ? to sck ? or sck ? input 2.25 t cy ??ns sp71* t sc h sck input high time (slave mode) 1 t cy + 20 ? ? ns sp72* t sc l sck input low time (slave mode) 1 t cy + 20 ? ? ns sp73* t di v2 sc h, t di v2 sc l setup time of sdi data input to sck edge 100 ? ? ns sp74* t sc h2 di l, t sc l2 di l hold time of sdi data input to sck edge 100 ? ? ns sp75* t do r sdo data output rise time ? 10 25 ns 3.0v ? v dd ? 5.5v ?2550ns1.8v ? v dd ? 5.5v sp76* t do f sdo data output fall time ? 10 25 ns sp77* t ss h2 do zss ? to sdo output high-impedance 10 ? 50 ns sp78* t sc r sck output rise time (master mode) ?1025ns3.0v ? v dd ? 5.5v ?2550ns1.8v ? v dd ? 5.5v sp79* t sc f sck output fall time (master mode) ? 10 25 ns sp80* t sc h2 do v, t sc l2 do v sdo data output valid after sck edge ? ? 50 ns 3.0v ? v dd ? 5.5v ??145ns1.8v ? v dd ? 5.5v sp81* t do v2 sc h, t do v2 sc l sdo data output setup to sck edge 1 tcy ? ? ns sp82* t ss l2 do v sdo data output valid after ss ? edge ??50ns sp83* t sc h2 ss h, t sc l2 ss h ss ?? after sck edge 1.5 t cy + 40 ? ? ns * these parameters are characterized but not tested. ? data in ?typ? column is at 3.0v, 25c unless otherwise stated. these parameters are for design guidance only and are not tested.
pic16(l)f1508/9 ds40001609b-page 350 ? 2011-2013 microchip technology inc. figure 29-20: i 2 c? bus start/stop bits timing table 29-20: i 2 c? bus start/stop bits requirements figure 29-21: i 2 c? bus data timing standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. typ max. units conditions sp90* t su : sta start condition 100 khz mode 4700 ? ? ns only relevant for repeated start condition setup time 400 khz mode 600 ? ? sp91* t hd : sta start condition 100 khz mode 4000 ? ? ns after this period, the first clock pulse is generated hold time 400 khz mode 600 ? ? sp92* t su : sto stop condition 100 khz mode 4700 ? ? ns setup time 400 khz mode 600 ? ? sp93 t hd : sto stop condition 100 khz mode 4000 ? ? ns hold time 400 khz mode 600 ? ? * these parameters are characterized but not tested. note : refer to figure 29-4 for load conditions. sp91 sp92 sp93 scl sda start condition stop condition sp90 note: refer to figure 29-4 for load conditions. sp90 sp91 sp92 sp100 sp101 sp103 sp106 sp107 sp109 sp109 sp110 sp102 scl sda in sda out
? 2011-2013 microchip technology inc. ds40001609b-page 351 pic16(l)f1508/9 table 29-21: i 2 c? bus data requirements standard operating conditions (unless otherwise stated) param. no. symbol characteristic min. max. units conditions sp100* t high clock high time 100 khz mode 4.0 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 0.6 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? sp101* t low clock low time 100 khz mode 4.7 ? ? s device must operate at a minimum of 1.5 mhz 400 khz mode 1.3 ? ? s device must operate at a minimum of 10 mhz ssp module 1.5t cy ? sp102* t r sda and scl rise time 100 khz mode ? 1000 ns 400 khz mode 20 + 0.1c b 300 ns c b is specified to be from 10-400 pf sp103* t f sda and scl fall time 100 khz mode ? 250 ns 400 khz mode 20 + 0.1c b 250 ns c b is specified to be from 10-400 pf sp106* t hd : dat data input hold time 100 khz mode 0 ? ns 400 khz mode 0 0.9 ? s sp107* t su : dat data input setup time 100 khz mode 250 ? ns (note 2) 400 khz mode 100 ? ns sp109* t aa output valid from clock 100 khz mode ? 3500 ns (note 1) 400 khz mode ? ? ns sp110* t buf bus free time 100 khz mode 4.7 ? ? s time the bus must be free before a new transmission can start 400 khz mode 1.3 ? ? s sp111 c b bus capacitive loading ? 400 pf * these parameters are characterized but not tested. note 1: as a transmitter, the device must provide this internal minimum delay time to bridge the undefined region (min. 300 ns) of the falling edge of scl to avoid unintended generation of start or stop conditions. 2: a fast mode (400 khz) i 2 c? bus device can be used in a standard mode (100 khz) i 2 c bus system, but the requirement t su : dat ?? 250 ns must then be met. this will automatically be the case if the device does not stretch the low period of the scl signal. if such a device does stretch the low period of the scl signal, it must output the next data bit to the sda line t r max. + t su : dat = 1000 + 250 = 1250 ns (according to the standard mode i 2 c bus specification), before the scl line is released.
pic16(l)f1508/9 ds40001609b-page 352 ? 2011-2013 microchip technology inc.
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 351 pic16(l)f1508/9 30.0 dc and ac characteristics graphs and charts the graphs and tables provided in this section are for design guidance and are not tested . in some graphs or tables, the data presented are outside specified operating range (i.e., outside specified v dd range). this is for information only and devices are ensured to operate properly only within the specified range. ? typical? represents the mean of the distribution at 25 ? c. ?maximum?, ?max.?, ?minimum? or ?min.? represents (mean + 3 ? ) or (mean - 3 ? ) respectively, where ? is a standard deviation, over each temperature range. note: the graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. the performance characteristics listed herein are not tested or guaranteed. in some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
pic16(l)f1508/9 ds40001609b-page 352 preliminary ? 2011-2013 microchip technology inc. figure 30-1: i dd , lp oscillator, f osc = 32 khz, pic16lf1508/9 only figure 30-2: i dd , lp oscillator, f osc = 32 khz, pic16f1508/9 only typical max. 0 2 4 6 8 10 12 14 16 18 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 353 pic16(l)f1508/9 figure 30-3: i dd typical, xt and extrc oscillator, pic16lf1508/9 only figure 30-4: i dd maximum, xt and extrc oscillator, pic16lf1508/9 only 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1
pic16(l)f1508/9 ds40001609b-page 354 preliminary ? 2011-2013 microchip technology inc. figure 30-5: i dd typical, xt and extrc oscillator, pic16f1508/9 only figure 30-6: i dd maximum, xt and extrc oscillator, pic16f1508/9 only 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz extrc 4 mhz xt 1 mhz extrc 1 mhz xt 0 50 100 150 200 250 300 350 400 450 500 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 355 pic16(l)f1508/9 figure 30-7: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic16lf1508/9 only figure 30-8: i dd , external clock (ecl), low-power mode, f osc = 32 khz, pic16f1508/9 only typical max. 0 2 4 6 8 10 12 14 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (a) v dd (v) max: 85c + 3 1 typical: 25c
pic16(l)f1508/9 ds40001609b-page 356 preliminary ? 2011-2013 microchip technology inc. figure 30-9: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic16lf1508/9 only figure 30-10: i dd , external clock (ecl), low-power mode, f osc = 500 khz, pic16f1508/9 only max. typical 0 5 10 15 20 25 30 35 40 45 50 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 10 20 30 40 50 60 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 357 pic16(l)f1508/9 figure 30-11: i dd typical, external clock (ecm), medium-power mode, pic16lf1508/9 only figure 30-12: i dd maximum, external clock (ecm), medium-power mode, pic16lf1508/9 only 4 mhz 1 mhz 0 50 100 150 200 250 300 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1
pic16(l)f1508/9 ds40001609b-page 358 preliminary ? 2011-2013 microchip technology inc. figure 30-13: i dd typical, external clock (ecm), medium-power mode, pic16f1508/9 only figure 30-14: i dd maximum, external clock (ecm), medium-power mode, pic16f1508/9 only 4 mhz 1 mhz 0 50 100 150 200 250 300 350 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) typical: 25c 4 mhz 1 mhz 0 50 100 150 200 250 300 350 400 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 359 pic16(l)f1508/9 figure 30-15: i dd typical, external clock (ech), high-power mode, pic16lf1508/9 only figure 30-16: i dd maximum, external clock (ech), high-power mode, pic16lf1508/9 only 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c () 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1
pic16(l)f1508/9 ds40001609b-page 360 preliminary ? 2011-2013 microchip technology inc. figure 30-17: i dd typical, external clock (ech), high-power mode, pic16f1508/9 only figure 30-18: i dd maximum, external clock (ech), high-power mode, pic16f1508/9 only 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 20 mhz 16 mhz 8 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 361 pic16(l)f1508/9 figure 30-19: i dd , lfintosc, f osc = 31 khz, pic16lf1508/9 only figure 30-20: i dd , lfintosc, f osc = 31 khz, pic16f1508/9 only typical max. 0 2 4 6 8 10 12 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 5 10 15 20 25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c
pic16(l)f1508/9 ds40001609b-page 362 preliminary ? 2011-2013 microchip technology inc. figure 30-21: i dd , mfintosc, f osc = 500 khz, pic16lf1508/9 only figure 30-22: i dd , mfintosc, f osc = 500 khz, pic16f1508/9 only typical max. 0 50 100 150 200 250 300 350 400 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 50 100 150 200 250 300 350 400 450 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd ( a) v dd (v) max: 85c + 3 1 typical: 25c
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 363 pic16(l)f1508/9 figure 30-23: i dd typical, hfintosc, pic16lf1508/9 only figure 30-24: i dd maximum, hfintosc, pic16lf1508/9 only 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1
pic16(l)f1508/9 ds40001609b-page 364 preliminary ? 2011-2013 microchip technology inc. figure 30-25: i dd typical, hfintosc, pic16f1508/9 only figure 30-26: i dd maximum, hfintosc, pic16f1508/9 only 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c 16 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 365 pic16(l)f1508/9 figure 30-27: i dd typical, hs oscillator, pic16lf1508/9 only figure 30-28: i dd maximum, hs oscillator, pic16lf1508/9 only 20 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) typical: 25c , 20 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i dd (ma) v dd (v) max: 85c + 3 1
pic16(l)f1508/9 ds40001609b-page 366 preliminary ? 2011-2013 microchip technology inc. figure 30-29: i dd typical, hs oscillator, pic16f1508/9 only figure 30-30: i dd maximum, hs oscillator, pic16f1508/9 only 20 mhz 8 mhz 4 mhz 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) typical: 25c , 20 mhz 8 mhz 4 mhz 0.0 0.5 1.0 1.5 2.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i dd (ma) v dd (v) max: 85c + 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 367 pic16(l)f1508/9 figure 30-31: i pd base, low-power sleep mode, pic16lf1508/9 only figure 30-32: i pd base, low-power sleep mode, vregpm = 1 , pic16f1508/9 only 450 m85 c3 max. 250 300 350 400 450 d (na) max: 85c + 3 1 typical: 25c typical 0 50 100 150 200 250 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd (na) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max. 600 max. 300 400 500 600 p d (na) max: 85c + 3 1 typical: 25c typical 0 100 200 300 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd (na) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic16(l)f1508/9 ds40001609b-page 368 preliminary ? 2011-2013 microchip technology inc. figure 30-33: i pd , watchdog timer (wdt), pic16lf1508/9 only figure 30-34: i pd , watchdog timer (wdt), pic16f1508/9 only 2.0 max. 08 1.0 1.2 1.4 1.6 1.8 2.0 i pd (a) max: 85c + 3 1 typical: 25c typical 0.0 0.2 0.4 0.6 0.8 1.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 0.2 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) max 1.4 typical max. 0.6 0.8 1.0 1.2 1.4 i pd ( a) typical 0.0 0.2 0.4 0.6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a max: 85c + 3 1 typical: 25c 0.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 369 pic16(l)f1508/9 figure 30-35: i pd , fixed voltage reference (fvr), pic16lf1508/9 only figure 30-36: i pd , fixed voltage reference (fvr), pic16f1508/9 only 45 max: 85 c+3 1 typical max. 20 25 30 35 40 45 i pd ( a) max: 85c + 3 1 typical: 25c 0 5 10 15 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 30 typical max. 15 20 25 30 i pd ( a) 0 5 10 15 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( max: 85c + 3 1 typical: 25c 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic16(l)f1508/9 ds40001609b-page 370 preliminary ? 2011-2013 microchip technology inc. figure 30-37: i pd , brown-out reset (bor), borv = 0 , pic16lf1508/9 only figure 30-38: i pd , brown-out reset (bor), borv = 1 , pic16lf1508/9 only max. 10 typical max. 4 5 6 7 8 9 10 d ( a) max: 85c + 3 1 typical: 25c 0 1 2 3 4 5 16 18 20 22 24 26 28 30 32 34 36 38 i pd ( a) 0 1 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 12 typical max. 6 8 10 12 a) max: 85c + 3 1 typical: 25c typical 0 2 4 6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a) 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v)
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 371 pic16(l)f1508/9 figure 30-39: i pd , brown-out reset (bor), borv = 0 , pic16f1508/9 only figure 30-40: i pd , brown-out reset (bor), borv = 1 , pic16f1508/9 only m 12 typical max. 6 8 10 12 i pd ( a) max: 85c + 3 1 typical: 25c 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a ) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v) max 14 typical max. 6 8 10 12 14 i pd ( a) max: 85c + 3 1 typical: 25c 0 2 4 6 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a ) 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic16(l)f1508/9 ds40001609b-page 372 preliminary ? 2011-2013 microchip technology inc. figure 30-41: i pd , secondary oscillator, f osc = 32 khz, pic16lf1508/9 only figure 30-42: i pd , secondary oscillator, f osc = 32 khz, pic16f1508/9 only 8.0 max: 85 c+3 1 max. 30 4.0 5.0 6.0 7.0 8.0 i pd ( a) max: 85c + 3 1 typical: 25c typical 0.0 1.0 2.0 3.0 4.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a 0.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 16 max: 85 c+3 1 typical max. 6 8 10 12 14 16 i pd ( a) max: 85c + 3 1 typical: 25c typical 0 2 4 6 8 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 373 pic16(l)f1508/9 figure 30-43: i pd , comparator, low-power mode (cxsp = 0 ), pic16lf1508/9 only figure 30-44: i pd , comparator, low-power mode (cxsp = 0 ), pic16f1508/9 only 14 typical max. 6 8 10 12 14 i pd ( a) typical 0 2 4 6 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd max: 85c + 3 1 typical: 25c 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) 30 typical max. 15 20 25 30 i pd ( a) yp 0 5 10 15 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( max: 85c + 3 1 typical: 25c 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
pic16(l)f1508/9 ds40001609b-page 374 preliminary ? 2011-2013 microchip technology inc. figure 30-45: i pd , comparator, normal-power mode (cxsp = 1 ), pic16lf1508/9 only figure 30-46: i pd , comparator, normal-power mode (cxsp = 1 ), pic16f1508/9 only 40 typical max. 15 20 25 30 35 40 i pd ( a) typical 0 5 10 15 20 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 i pd ( a max: 85c + 3 1 typical: 25c 0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 v dd (v) typical: 25 c 60 typical max. 30 40 50 60 i pd ( a) typical 0 10 20 30 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 i pd ( a max: 85c + 3 1 typical: 25c 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 v dd (v)
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 375 pic16(l)f1508/9 figure 30-47: v oh vs. i oh over temperature, v dd = 5.5v, pic16f1508/9 only figure 30-48: v ol vs. i ol over temperature, v dd = 5.5v, pic16f1508/9 only min. (-40c) typical (25c) max. (125c) 0 1 2 3 4 5 6 -45 -40 -35 -30 -25 -20 -15 -10 -5 0 v oh (v) i oh (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1 min. (-40c) typical (25c) max. (125c) 0 1 2 3 4 5 0 102030405060708090100 v ol (v) i ol (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1
pic16(l)f1508/9 ds40001609b-page 376 preliminary ? 2011-2013 microchip technology inc. figure 30-49: v oh vs. i oh over temperature, v dd = 3.0v figure 30-50: v ol vs. i ol over temperature, v dd = 3.0v min. (-40c) typical (25c) max. (125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 -15-13-11-9-7-5-3-1 v oh (v) i oh (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1 min. (-40c) typical (25c) max. (125c) 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0 5 10 15 20 25 30 35 40 v ol (v) i ol (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 377 pic16(l)f1508/9 figure 30-51: v oh vs. i oh over temperature, v dd = 1.8v, pic16lf1508/9 only figure 30-52: v ol vs. i ol over temperature, v dd = 1.8v, pic16lf1508/9 only min. (-40c) typical (25c) max. (125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 -4.5 -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -0.5 0.0 v oh (v) i oh (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1 min. (-40c) typical (25c) max. (125c) 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 012345678910 v ol (v) i ol (ma) max: 125c + 3 1 typical: 25c min: -40c - 3 1
pic16(l)f1508/9 ds40001609b-page 378 preliminary ? 2011-2013 microchip technology inc. figure 30-53: por release voltage figure 30-54: por rearm voltage, pic16f1508/9 only typical max. min. 1.50 1.52 1.54 1.56 1.58 1.60 1.62 1.64 1.66 1.68 1.70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1 typical max. min. 1.34 1.36 1.38 1.40 1.42 1.44 1.46 1.48 1.50 1.52 1.54 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 379 pic16(l)f1508/9 figure 30-55: brown-out reset voltage, borv = 1 , pic16lf1508/9 only figure 30-56: brown-out reset hysteresis, borv = 1 , pic16lf1508/9 only typical max. min. 1.80 1.85 1.90 1.95 2.00 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1
pic16(l)f1508/9 ds40001609b-page 380 preliminary ? 2011-2013 microchip technology inc. figure 30-57: brown-out reset voltage, borv = 1 , pic16f1508/9 only figure 30-58: brown-out reset hysteresis, borv = 1 , pic16f1508/9 only typical max. min. 2.30 2.35 2.40 2.45 2.50 2.55 2.60 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 70 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 381 pic16(l)f1508/9 figure 30-59: brown-out reset voltage, borv = 0 figure 30-60: brown-out reset hysteresis, borv = 0 typical max. min. 2.55 2.60 2.65 2.70 2.75 2.80 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 10 20 30 40 50 60 70 80 90 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1
pic16(l)f1508/9 ds40001609b-page 382 preliminary ? 2011-2013 microchip technology inc. figure 30-61: low-power brown-out reset voltage, lpbor = 0 figure 30-62: low-power brown-out reset hysteresis, lpbor = 0 typical max. min. 1.80 1.90 2.00 2.10 2.20 2.30 2.40 2.50 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (v) temperature (c) max: typical + 3 1 min: typical - 3 1 typical max. min. 0 5 10 15 20 25 30 35 40 45 -60 -40 -20 0 20 40 60 80 100 120 140 voltage (mv) temperature (c) max: typical + 3 1 typical: 25c min: typical - 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 383 pic16(l)f1508/9 figure 30-63: wdt time-out period figure 30-64: pwrt period typical max. min. 10 12 14 16 18 20 22 24 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) typical max. min. 40 50 60 70 80 90 100 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ms) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c)
pic16(l)f1508/9 ds40001609b-page 384 preliminary ? 2011-2013 microchip technology inc. figure 30-65: fvr stabilization period typical max. 0 10 20 30 40 50 60 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 time (us) v dd (v) max: typical + 3 1 typical: statistical mean @ 25c note: the fvr stabilization period applies when: 1) coming out of reset or exiting sleep mode for pic12/16lfxxxx devices. 2) when exiting sleep mode with vregpm = 1 for pic12/16fxxxx devices in all other cases, the fvr is stable when released from reset.
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 385 pic16(l)f1508/9 figure 30-66: comparator hysteresis, normal-power mode (cxsp = 1 , cxhys = 1 ) figure 30-67: comparator hysteresis, low-power mode (cxsp = 0 , cxhys = 1 ) min. typical max. 0 5 10 15 20 25 30 35 40 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 hysteresis (mv) v dd (v) max: typical + 3 1 typical: 25c min: typical - 3 1 min. typical max. 0 1 2 3 4 5 6 7 8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 hysteresis (mv) v dd (v) max: typical + 3 1 typical: 25c min: typical - 3 1
pic16(l)f1508/9 ds40001609b-page 386 preliminary ? 2011-2013 microchip technology inc. figure 30-68: comparator response time, normal-power mode (cxsp = 1 ) figure 30-69: comparator response time over temperature, normal-power mode (cxsp = 1 ) max. typical 0 50 100 150 200 250 300 350 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ns) v dd (v) max: typical + 3 1 typical: 25c min. (-40c) typical (25c) max. (125c) 0 50 100 150 200 250 300 350 400 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (ns) v dd (v) max: 125c + 3 1 typical: 25c min: -45c - 3 1
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 387 pic16(l)f1508/9 figure 30-70: comparator input offset at 25c, normal-power mode (cxsp = 1 ), pic16f1508/9 only max. typical min. -50 -40 -30 -20 -10 0 10 20 30 40 50 0.0 1.0 2.0 3.0 4.0 5.0 offset voltage (mv) common mode voltage (v) max: typical + 3 1 typical: 25c min: typical - 3 1
pic16(l)f1508/9 ds40001609b-page 388 preliminary ? 2011-2013 microchip technology inc. figure 30-71: lfintosc frequency over v dd and temperature, pic16lf1508/9 only figure 30-72: lfintosc frequency over v dd and temperature, pic16f1508/9 only typical max. min. 20 22 24 26 28 30 32 34 36 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 frequency (khz) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c) typical max. min. 20 22 24 26 28 30 32 34 36 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 frequency (khz) v dd (v) max: typical + 3 1 (-40c to +125c) typical: statistical mean @ 25c min: typical - 3 1 (-40c to +125c)
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 389 pic16(l)f1508/9 figure 30-73: hfintosc accuracy over temperature, v dd = 1.8v, pic16lf1508/9 only figure 30-74: hfintosc accuracy over temperature, 2.3v ? v dd ?? 5.5v typical max. min. -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% -60 -40 -20 0 20 40 60 80 100 120 140 accuracy (%) temperature (c) max: typical + 3 1 typical: statistical mean min: typical - 3 1 typical max. min. -10% -8% -6% -4% -2% 0% 2% 4% 6% 8% -60 -40 -20 0 20 40 60 80 100 120 140 accuracy (%) temperature (c) max: typical + 3 1 typical: statistical mean min: typical - 3 1
pic16(l)f1508/9 ds40001609b-page 390 preliminary ? 2011-2013 microchip technology inc. figure 30-75: sleep mode, wake period with hfintosc source, pic16lf1508/9 only typical max. 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 3.4 3.6 3.8 time (us) v dd (v) max: 85c + 3 1 typical: 25c
? 2011-2013 microchip technology inc. preliminary ds40001609b-page 391 pic16(l)f1508/9 figure 30-76: low-power sleep mode, wake period with hfintosc source, vregpm = 1 , pic16f1508/9 only figure 30-77: sleep mode, wake peri od with hfintosc source, vregpm = 0 , pic16f1508/9 only typical max. 0 5 10 15 20 25 30 35 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (us) v dd (v) max: 85c + 3 1 typical: 25c typical max. 0 2 4 6 8 10 12 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 time (us) v dd (v) max: 85c + 3 1 typical: 25c
pic16(l)f1508/9 ds40001609b-page 392 preliminary ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 393 pic16(l)f1508/9 31.0 development support the pic ? microcontrollers (mcu) and dspic ? digital signal controllers (dsc) are supported with a full range of software and hardware development tools: ? integrated development environment - mplab ? x ide software ? compilers/assemblers/linkers - mplab xc compiler - mpasm tm assembler -mplink tm object linker/ mplib tm object librarian - mplab assembler/linker/librarian for various device families ? simulators - mplab x sim software simulator ?emulators - mplab real ice? in-circuit emulator ? in-circuit debuggers/programmers - mplab icd 3 - pickit? 3 ? device programmers - mplab pm3 device programmer ? low-cost demonstration/development boards, evaluation kits and starter kits ? third-party development tools 31.1 mplab x integrated development environment software the mplab x ide is a single, unified graphical user interface for microchip and third-party software, and hardware development tool that runs on windows ? , linux and mac os ? x. based on the netbeans ide, mplab x ide is an entirely new ide with a host of free software components and plug-ins for high- performance application development and debugging. moving between tools and upgrading from software simulators to hardware debugging and programming tools is simple with the seamless user interface. with complete project management, visual call graphs, a configurable watch window and a feature-rich editor that includes code completion and context menus, mplab x ide is flexible and friendly enough for new users. with the ability to support multiple tools on multiple projects with simultaneous debugging, mplab x ide is also suitable for the needs of experienced users. feature-rich editor: ? color syntax highlighting ? smart code completion makes suggestions and provides hints as you type ? automatic code formatting based on user-defined rules ? live parsing user-friendly, customizable interface: ? fully customizable interface: toolbars, toolbar buttons, windows, window placement, etc. ? call graph window project-based workspaces: ? multiple projects ? multiple tools ? multiple configurations ? simultaneous debugging sessions file history and bug tracking: ? local file history feature ? built-in support for bugzilla issue tracker
pic16(l)f1508/9 ds40001609b-page 394 ? 2011-2013 microchip technology inc. 31.2 mplab xc compilers the mplab xc compilers are complete ansi c compilers for all of microchip?s 8, 16, and 32-bit mcu and dsc devices. these compilers provide powerful integration capabilities, superior code optimization and ease of use. mplab xc compilers run on windows, linux or mac os x. for easy source level debugging, the compilers provide debug information that is optimized to the mplab x ide. the free mplab xc compiler editions support all devices and commands, with no time or memory restrictions, and offer sufficient code optimization for most applications. mplab xc compilers include an assembler, linker and utilities. the assembler generates relocatable object files that can then be archived or linked with other relo- catable object files and archives to create an execut- able file. mplab xc compiler uses the assembler to produce its object file. notable features of the assem- bler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility 31.3 mpasm assembler the mpasm assembler is a full-featured, universal macro assembler for pic10/12/16/18 mcus. the mpasm assembler generates relocatable object files for the mplink object linker, intel ? standard hex files, map files to detail memory usage and symbol reference, absolute lst files that contain source lines and generated machine code, and coff files for debugging. the mpasm assembler features include: ? integration into mplab x ide projects ? user-defined macros to streamline assembly code ? conditional assembly for multipurpose source files ? directives that allow complete control over the assembly process 31.4 mplink object linker/ mplib object librarian the mplink object linker combines relocatable objects created by the mpasm assembler. it can link relocatable objects from precompiled libraries, using directives from a linker script. the mplib object librarian manages the creation and modification of library files of precompiled code. when a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. this allows large libraries to be used efficiently in many different applications. the object linker/library features include: ? efficient linking of single libraries instead of many smaller files ? enhanced code maintainability by grouping related modules together ? flexible creation of libraries with easy module listing, replacement, deletion and extraction 31.5 mplab assembler, linker and librarian for various device families mplab assembler produces relocatable machine code from symbolic assembly language for pic24, pic32 and dspic dsc devices. mplab xc compiler uses the assembler to produce its object file. the assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. notable features of the assembler include: ? support for the entire device instruction set ? support for fixed-point and floating-point data ? command-line interface ? rich directive set ? flexible macro language ? mplab x ide compatibility
? 2011-2013 microchip technology inc. ds40001609b-page 395 pic16(l)f1508/9 31.6 mplab x sim software simulator the mplab x sim software simulator allows code development in a pc-hosted environment by simulat- ing the pic mcus and dspic dscs on an instruction level. on any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. registers can be logged to files for further run-time analysis. the trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on i/o, most peripherals and internal registers. the mplab x sim software simulator fully supports symbolic debugging using the mplab xc compilers, and the mpasm and mplab assemblers. the soft- ware simulator offers the flexibility to develop and debug code outside of the hardware laboratory envi- ronment, making it an excellent, economical software development tool. 31.7 mplab real ice in-circuit emulator system the mplab real ice in-circuit emulator system is microchip?s next generation high-speed emulator for microchip flash dsc and mcu devices. it debugs and programs all 8, 16 and 32-bit mcu, and dsc devices with the easy-to-use, powerful graphical user interface of the mplab x ide. the emulator is connected to the design engineer?s pc using a high-speed usb 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (rj-11) or with the new high-speed, noise tolerant, low- voltage differential signal (lvds) interconnection (cat5). the emulator is field upgradable through future firmware downloads in mplab x ide. mplab real ice offers significant advantages over competitive emulators including full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, logic probes, a ruggedized probe interface and long (up to three meters) interconnection cables. 31.8 mplab icd 3 in-circuit debugger system the mplab icd 3 in-circuit debugger system is microchip?s most cost-effective, high-speed hardware debugger/programmer for microchip flash dsc and mcu devices. it debugs and programs pic flash microcontrollers and dspic dscs with the powerful, yet easy-to-use graphical user interface of the mplab ide. the mplab icd 3 in-circuit debugger probe is connected to the design engineer?s pc using a high- speed usb 2.0 interface and is connected to the target with a connector compatible with the mplab icd 2 or mplab real ice systems (rj-11). mplab icd 3 supports all mplab icd 2 headers. 31.9 pickit 3 in-circuit debugger/ programmer the mplab pickit 3 allows debugging and program- ming of pic and dspic flash microcontrollers at a most affordable price point using the powerful graphical user interface of the mplab ide. the mplab pickit 3 is connected to the design engineer?s pc using a full- speed usb interface and can be connected to the tar- get via a microchip debug (rj-11) connector (compati- ble with mplab icd 3 and mplab real ice). the connector uses two device i/o pins and the reset line to implement in-circuit debugging and in-circuit serial programming? (icsp?). 31.10 mplab pm3 device programmer the mplab pm3 device programmer is a universal, ce compliant device programmer with programmable voltage verification at v ddmin and v ddmax for maximum reliability. it features a large lcd display (128 x 64) for menus and error messages, and a mod- ular, detachable socket assembly to support various package types. the icsp cable assembly is included as a standard item. in stand-alone mode, the mplab pm3 device programmer can read, verify and program pic devices without a pc connection. it can also set code protection in this mode. the mplab pm3 connects to the host pc via an rs-232 or usb cable. the mplab pm3 has high-speed communications and optimized algorithms for quick programming of large memory devices, and incorporates an mmc card for file storage and data applications.
pic16(l)f1508/9 ds40001609b-page 396 ? 2011-2013 microchip technology inc. 31.11 demonstration/development boards, evaluation kits, and starter kits a wide variety of demonstration, development and evaluation boards for various pic mcus and dspic dscs allows quick application development on fully functional systems. most boards include prototyping areas for adding custom circuitry and provide applica- tion firmware and source code for examination and modification. the boards support a variety of features, including leds, temperature sensors, switches, speakers, rs-232 interfaces, lcd displays, potentiometers and additional eeprom memory. the demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. in addition to the picdem? and dspicdem? demonstration/development board series of circuits, microchip has a line of evaluation kits and demonstra- tion software for analog filter design, k ee l oq ? security ics, can, irda ? , powersmart battery management, seeval ? evaluation system, sigma-delta adc, flow rate sensing, plus many more. also available are starter kits that contain everything needed to experience the specified device. this usually includes a single application and debug capability, all on one board. check the microchip web page ( www.microchip.com ) for the complete list of demonstration, development and evaluation kits. 31.12 third-party development tools microchip also offers a great collection of tools from third-party vendors. these tools are carefully selected to offer good value and unique functionality. ? device programmers and gang programmers from companies, such as softlog and ccs ? software tools from companies, such as gimpel and trace systems ? protocol analyzers from companies, such as saleae and total phase ? demonstration boards from companies, such as mikroelektronika, digilent ? and olimex ? embedded ethernet solutions from companies, such as ez web lynx, wiznet and iplogika ?
? 2011-2013 microchip technology inc. ds40001609b-page 397 pic16(l)f1508/9 32.0 packaging information 32.1 package marking information * standard picmicro ? device marking consists of microchip part number, year code, week code and traceability code. for picmicro device marking beyond this, certain price adders apply. please check with your microchip sales office. for qtp devices, any special marking adders are included in qtp price. legend: xx...x customer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec designator for matte tin (sn) * this package is pb-free. the pb-free jedec designator ( ) can be found on the outer packaging for this package. note : in the event the full microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 3 e 3 e 20-lead pdip (300 mil) example xxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxx yywwnnn pic16f1508 -e/p 3 e 1120123 20-lead soic (7.50 mm) example pic16f1508 -e/so 3 e 1120123
pic16(l)f1508/9 ds40001609b-page 398 ? 2011-2013 microchip technology inc. 32.2 package marking information 20-lead ssop (5.30 mm) example 20-lead qfn (4x4x0.9 mm) example pin 1 pin 1 -e/ss 3 e 1120123 pic16f1508 pic16 f1508 e/ml 120123 3 e
? 2011-2013 microchip technology inc. ds40001609b-page 399 pic16(l)f1508/9 32.3 package details the following sections give the technical details of the packages.

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? 2011-2013 microchip technology inc. ds40001609b-page 401 pic16(l)f1508/9 note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging
pic16(l)f1508/9 ds40001609b-page 402 ? 2011-2013 microchip technology inc.
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pic16(l)f1508/9 ds40001609b-page 406 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 407 pic16(l)f1508/9 appendix a: data sheet revision history revision a (10/2011) original release. revision b (6/2013) updated electrical specifications and added characterization data.
pic16(l)f1508/9 ds40001609b-page 408 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 409 pic16(l)f1508/9 index a absolute maximum ratings .............................................. 321 ac characteristics load conditions ........................................................ 333 ackstat ......................................................................... 215 ackstat status flag ...................................................... 215 adc .................................................................................. 133 acquisition requirements ......................................... 144 associated registers.................................................. 146 block diagram........................................................... 133 calculating acquisition time..................................... 144 channel selection..................................................... 134 configuration............................................................. 134 configuring interrupt ................................................. 138 conversion clock...................................................... 134 conversion procedure .............................................. 138 internal sampling switch (r ss ) impedance.............. 144 interrupts................................................................... 136 operation .................................................................. 137 operation during sleep ............................................ 137 port configuration ..................................................... 134 reference voltage (v ref )......................................... 134 source impedance.................................................... 144 specifications............................................................ 342 starting an adc conversion..................................... 136 adcon0 register....................................................... 27, 139 adcon1 register....................................................... 27, 140 adcon2 register....................................................... 27, 141 addfsr ........................................................................... 311 addwfc .......................................................................... 311 adresh register (adfm = 0) ......................................... 142 adresh register (adfm = 1) ......................................... 143 adresl register ............................................................... 27 adresl register (adfm = 0).......................................... 142 adresl register (adfm = 1).......................................... 143 alternate pin function....................................................... 110 analog-to-digital converter. see adc ansela register ............................................................. 113 anselb register ............................................................. 117 anselc register ............................................................. 121 apfcon register............................................................. 110 assembler mpasm assembler................................................... 394 automatic context saving................................................... 75 b bank 10............................................................................... 30 bank 11............................................................................... 30 bank 12............................................................................... 30 bank 13............................................................................... 30 bank 2................................................................................. 28 bank 3................................................................................. 28 bank 30............................................................................... 31 bank 4................................................................................. 29 bank 5................................................................................. 29 bank 6................................................................................. 29 bank 7................................................................................. 29 bank 8................................................................................. 29 bank 9................................................................................. 29 baudcon register.......................................................... 247 bf ............................................................................. 215, 217 bf status flag .......................................................... 215, 217 block diagrams adc .......................................................................... 133 adc transfer function............................................. 145 analog input model........................................... 145, 153 block diagrams pic16(l)1508/9 .................................................... 3 clock source .............................................................. 48 comparator............................................................... 151 crystal operation.................................................. 50, 51 digital-to-analog converter (dac) ........................... 147 eusart receive ..................................................... 236 eusart transmit .................................................... 235 external rc mode ...................................................... 51 fail-safe clock monitor (fscm)................................. 58 generic i/o port........................................................ 109 interrupt logic............................................................. 71 nco.......................................................................... 286 on-chip reset circuit................................................. 63 pic16(l)f1508/9 .......................................................... 8 pwm......................................................................... 263 resonator operation .................................................. 50 timer0 ...................................................................... 159 timer1 ...................................................................... 163 timer1 gate.............................................. 168, 169, 170 timer2 ...................................................................... 175 voltage reference.................................................... 129 borcon register.............................................................. 65 bra .................................................................................. 312 break character (12-bit) transmit and receive ............... 256 brown-out reset (bor) ..................................................... 65 specifications ........................................................... 338 timing and characteristics ....................................... 337 brw ................................................................................. 312 c c compilers mplab c18.............................................................. 394 call................................................................................. 313 callw ............................................................................. 313 clcdata register........................................................... 283 clcxcon register .......................................................... 275 clcxgls0 register ......................................................... 279 clcxgls1 register ......................................................... 280 clcxgls2 register ......................................................... 281 clcxgls3 register ......................................................... 282 clcxpol register ........................................................... 276 clcxsel0 register.......................................................... 277 clock accuracy with asynchronous operation ................. 244 clock sources external modes........................................................... 49 ec ...................................................................... 49 hs ...................................................................... 49 lp ....................................................................... 49 ost .................................................................... 50 rc ...................................................................... 51 xt ....................................................................... 49 internal modes............................................................ 52 frc .................................................................... 52 hfintosc ......................................................... 52 internal oscillator clock switch timing .............. 53 lfintosc.......................................................... 52 clock switching .................................................................. 55 cmout register .............................................................. 156 cmxcon0 register .......................................................... 155 cmxcon1 register .......................................................... 156
pic16(l)f1508/9 ds40001609b-page 410 ? 2011-2013 microchip technology inc. code examples adc conversion ....................................................... 138 initializing porta..................................................... 111 writing to flash program memory ............................ 102 comparator associated registers ................................................ 157 operation .................................................................. 151 comparator module .......................................................... 151 cx output state versus input conditions ................. 153 comparator specifications ................................................ 343 comparators c2out as t1 gate ................................................... 165 complementary waveform generator (cwg) .......... 293, 294 config1 register.............................................................. 42 config2 register.............................................................. 44 core function register ....................................................... 26 customer change notification service ............................. 415 customer notification service........................................... 415 customer support ............................................................. 415 cwg auto-shutdown control ............................................. 297 clock source............................................................. 293 output control........................................................... 293 selectable input sources .......................................... 293 cwgxcon0 register ....................................................... 300 cwgxcon1 register ....................................................... 301 cwgxcon2 register ....................................................... 302 cwgxdbf register .......................................................... 303 cwgxdbr register.......................................................... 303 d dacxcon0 (digital-to-analog converter control 0) register..................................................................... 149 dacxcon1 (digital-to-analog converter control 1) register..................................................................... 149 data memory....................................................................... 18 dc and ac characteristics ............................................... 351 dc characteristics extended and industrial ............................................ 330 industrial and extended ............................................ 323 development support ....................................................... 393 device configuration........................................................... 41 code protection .......................................................... 45 configuration word ..................................................... 41 user id .................................................................. 45, 46 device id register .............................................................. 46 device overview ............................................................. 7, 89 digital-to-analog converter (dac).................................... 147 associated registers ................................................ 149 effects of a reset...................................................... 147 specifications............................................................ 343 e effects of reset pwm mode ............................................................... 265 electrical specifications .................................................... 321 enhanced mid-range cpu................................................. 13 enhanced universal synchronous asynchronous receiver transmitter (eusart)............................... 235 errata .................................................................................... 6 eusart............................................................................ 235 associated registers baud rate generator........................................ 249 asynchronous mode ................................................. 237 12-bit break transmit and receive................... 256 associated registers receive .................................................... 243 transmit.................................................... 239 auto-wake-up on break ................................... 254 baud rate generator (brg) ............................ 248 clock accuracy................................................. 244 receiver ........................................................... 240 setting up 9-bit mode with address detect ...... 242 transmitter ....................................................... 237 baud rate generator (brg) auto baud rate detect..................................... 253 baud rate error, calculating............................ 248 baud rates, asynchronous modes .................. 250 formulas........................................................... 249 high baud rate select (brgh bit) .................. 248 synchronous master mode............................... 257, 261 associated registers receive .................................................... 260 transmit.................................................... 258 reception ......................................................... 259 transmission .................................................... 257 synchronous slave mode associated registers receive .................................................... 262 transmit.................................................... 261 reception ......................................................... 262 transmission .................................................... 261 f fail-safe clock monitor ...................................................... 58 fail-safe condition clearing....................................... 58 fail-safe detection ..................................................... 58 fail-safe operation..................................................... 58 reset or wake-up from sleep .................................... 59 firmware instructions ....................................................... 307 fixed voltage reference (fvr)........................................ 129 associated registers ................................................ 130 flash program memory ...................................................... 93 associated registers ................................................ 108 configuration word w/ flash program memory........ 108 erasing ....................................................................... 97 modifying .................................................................. 103 write verify ............................................................... 105 writing ........................................................................ 99 fsr register ...................................................................... 26 fvrcon (fixed voltage reference control) register..... 130 i i 2 c mode (msspx) acknowledge sequence timing ............................... 219 bus collision during a repeated start condition................... 224 during a stop condition ................................... 225 effects of a reset ..................................................... 220 i 2 c clock rate w/brg.............................................. 227 master mode operation.......................................................... 211 reception ......................................................... 217 start condition timing .............................. 213, 214 transmission .................................................... 215 multi-master communication, bus collision and arbitration ......................................................... 220 multi-master mode .................................................... 220 read/write bit information (r/w bit)........................ 195 slave mode transmission .................................................... 201 sleep operation........................................................ 220
? 2011-2013 microchip technology inc. ds40001609b-page 411 pic16(l)f1508/9 stop condition timing............................................... 219 indf register ..................................................................... 26 indirect addressing ............................................................. 36 instruction format ............................................................. 308 instruction set ................................................................... 307 addlw ..................................................................... 311 addwf..................................................................... 311 addwfc .................................................................. 311 andlw ..................................................................... 311 andwf..................................................................... 311 bcf........................................................................... 312 bra........................................................................... 312 brw.......................................................................... 312 bsf ........................................................................... 312 btfsc ...................................................................... 312 btfss ...................................................................... 312 call ......................................................................... 313 callw...................................................................... 313 clrf......................................................................... 313 clrw ....................................................................... 313 clrwdt................................................................... 313 comf ....................................................................... 313 decf ........................................................................ 313 decfsz.................................................................... 314 goto ....................................................................... 314 incf.......................................................................... 314 incfsz ..................................................................... 314 iorlw ...................................................................... 314 iorwf ...................................................................... 314 lslf ......................................................................... 315 lsrf......................................................................... 315 movf........................................................................ 315 moviw ..................................................................... 316 movlb ..................................................................... 316 movlp ..................................................................... 316 movlw .................................................................... 316 movwf .................................................................... 316 movwi ..................................................................... 317 nop .......................................................................... 317 option .................................................................... 317 reset ...................................................................... 317 retfie ..................................................................... 318 retlw ..................................................................... 318 return ................................................................... 318 rlf ........................................................................... 318 rrf........................................................................... 319 sleep ...................................................................... 319 sublw ..................................................................... 319 subwf ..................................................................... 319 subwfb................................................................... 319 swapf ..................................................................... 320 tris.......................................................................... 320 xorlw..................................................................... 320 xorwf..................................................................... 320 intcon register................................................................ 76 internal oscillator block intosc specifications.................................................... 335 internal sampling switch (r ss ) impedance ...................... 144 internet address................................................................ 415 interrupt-on-change ......................................................... 123 associated registers ................................................ 127 interrupts............................................................................. 71 adc .......................................................................... 138 associated registers w/ interrupts............................... 83 configuration word w/ clock sources........................ 62 tmr1........................................................................ 167 intosc specifications ..................................................... 335 iocaf register ................................................................ 125 iocan register ................................................................ 125 iocap register ................................................................ 125 iocbf register ................................................................ 126 iocbn register ................................................................ 126 iocbp register ................................................................ 126 l lata register .......................................................... 113, 120 latb register .................................................................. 117 load conditions................................................................ 333 lslf ................................................................................. 315 lsrf ................................................................................ 315 m master synchronous serial port. see msspx mclr ................................................................................. 66 internal........................................................................ 66 memory organization ......................................................... 15 data ............................................................................ 18 program...................................................................... 15 microchip internet web site.............................................. 415 moviw ............................................................................. 316 movlb ............................................................................. 316 movlp ............................................................................. 316 movwi ............................................................................. 317 mplab asm30 assembler, linker, librarian ................... 394 mplab integrated development environment software.. 393 mplab pm3 device programmer .................................... 395 mplab real ice in-circuit emulator system ................ 395 mplink object linker/mplib object librarian ................ 394 msspx.............................................................................. 179 spi mode.................................................................. 182 sspxbuf register ................................................... 186 sspxsr register ..................................................... 186 n nco associated registers ................................................. 291 ncoxacch register ....................................................... 290 ncoxaccl register ........................................................ 290 ncoxaccu register ....................................................... 290 ncoxclk register........................................................... 289 ncoxcon register.......................................................... 289 ncoxinch register......................................................... 291 ncoxincl register ......................................................... 291 numerically controlled oscillator (nco) .......................... 285 o opcode field descriptions............................................. 307 option ............................................................................ 317 option register.............................................................. 161 osccon register.............................................................. 60 oscillator associated registers.................................................. 62 associated registers ................................................. 304 oscillator module ................................................................ 47 ech ............................................................................ 47 ecl............................................................................. 47 ecm............................................................................ 47 hs............................................................................... 47 intosc ...................................................................... 47 lp ............................................................................... 47
pic16(l)f1508/9 ds40001609b-page 412 ? 2011-2013 microchip technology inc. rc............................................................................... 47 xt ............................................................................... 47 oscillator parameters........................................................ 335 oscillator specifications .................................................... 334 oscillator start-up timer (ost) specifications............................................................ 338 oscillator switching fail-safe clock monitor............................................... 58 two-speed clock start-up .......................................... 56 oscstat register............................................................. 61 p packaging ......................................................................... 397 marking ............................................................. 397, 398 pdip details.............................................................. 399 pcl and pclath ............................................................... 13 pcl register....................................................................... 26 pclath register................................................................ 26 pcon register ............................................................. 27, 69 pie1 register ................................................................ 27, 77 pie2 register ................................................................ 27, 78 pie3 register ................................................................ 27, 79 pinout descriptions pic16(l)f1508/9 .......................................................... 9 pir1 register................................................................ 27, 80 pir2 register................................................................ 27, 81 pir3 register................................................................ 27, 82 pmadr registers ............................................................... 93 pmadrh registers ............................................................ 93 pmadrl register............................................................. 106 pmadrl registers ............................................................. 93 pmcon1 register ...................................................... 93, 107 pmcon2 register ...................................................... 93, 108 pmdath register............................................................. 106 pmdatl register ............................................................. 106 pmdrh register............................................................... 106 porta.............................................................................. 111 associated registers ................................................ 114 lata register............................................................. 28 porta register ......................................................... 27 specifications............................................................ 336 porta register ............................................................... 112 portb.............................................................................. 115 associated registers ................................................ 118 latb register............................................................. 28 portb register ......................................................... 27 portb register ............................................................... 116 portc associated registers ................................................ 121 latc register ............................................................ 28 pin descriptions and diagrams................................. 119 portc register ......................................................... 27 portc register ............................................................... 120 power-down mode (sleep) ................................................. 85 associated registers .................................................. 87 power-on reset .................................................................. 64 power-up timer (pwrt)..................................................... 64 specifications............................................................ 338 pr2 register....................................................................... 27 program memory ................................................................ 15 map and stack (pic16(l)f1508 ................................. 16 map and stack (pic16(l)f1509 ................................. 16 programming mode exit...................................................... 66 programming, device instructions .................................... 307 pulse width modulation (pwm) ........................................ 263 associated registers w/ pwm ................................... 268 pwm mode duty cycle ........................................................ 264 effects of reset ................................................ 265 example pwm frequencies and resolutions, 20 mhz ................................ 265 example pwm frequencies and resolutions, 8 mhz .................................. 265 operation in sleep mode.................................. 265 setup for operation using pwmx pins ............. 266 system clock frequency changes .................. 265 pwm period.............................................................. 264 setup for pwm operation using pwmx pins ........... 266 pwmxcon register......................................................... 267 pwmxdch register ......................................................... 268 pwmxdcl register.......................................................... 268 r rcreg............................................................................. 242 rcreg register ................................................................ 28 rcsta register ......................................................... 28, 246 reader response............................................................. 416 read-modify-write operations ......................................... 307 registers adcon0 (adc control 0) ........................................ 139 adcon1 (adc control 1) ........................................ 140 adcon2 (adc control 2) ........................................ 141 adresh (adc result high) with adfm = 0) .......... 142 adresh (adc result high) with adfm = 1) .......... 143 adresl (adc result low) with adfm = 0)............ 142 adresl (adc result low) with adfm = 1)............ 143 ansela (porta analog select)............................. 113 anselb (portb analog select)............................. 117 anselc (portc analog select) ............................ 121 apfcon (alternate pin function control) ............... 110 baudcon (baud rate control)............................... 247 borcon (brown-out reset control) ......................... 65 clcdata (data output) .......................................... 283 clcxcon (clcx control)........................................ 275 clcxgls0 (gate 1 logic select)............................. 279 clcxgls1 (gate 2 logic select)............................. 280 clcxgls2 (gate 3 logic select)............................. 281 clcxgls3 (gate 4 logic select)............................. 282 clcxpol (signal polarity control)........................... 276 clcxsel0 (multiplexer data 1 and 2 select)........... 277 cmout (comparator output) .................................. 156 cmxcon0 (cx control) ............................................ 155 cmxcon1 (cx control 1) ......................................... 156 configuration word 1.................................................. 42 configuration word 2.................................................. 44 core function, summary............................................ 26 cwgxcon0 (cwg control 0) ................................. 300 cwgxcon1 (cwg control 1) ................................. 301 cwgxcon2 (cwg control 1) ................................. 302 cwgxdbf (cwgx dead band falling count)......... 303 cwgxdbr (cwgx dead band rising count) ......... 303 dacxcon0 .............................................................. 149 dacxcon1 .............................................................. 149 device id .................................................................... 46 fvrcon................................................................... 130 intcon (interrupt control)......................................... 76 iocaf (interrupt-on-change porta flag).............. 125 iocan (interrupt-on-change porta negative edge)................................................. 125 iocap (interrupt-on-change porta positive edge) .................................................. 125 iocbf (interrupt-on-change portb flag).............. 126
? 2011-2013 microchip technology inc. ds40001609b-page 413 pic16(l)f1508/9 iocbn (interrupt-on-change portb negative edge) ................................................. 126 iocbp (interrupt-on-change portb positive edge)................................................... 126 lata (data latch porta)....................................... 113 latb (data latch portb)....................................... 117 latc (data latch portc) ...................................... 120 ncoxacch (ncox accumulator high byte) ........... 290 ncoxaccl (ncox accumulator low byte)............. 290 ncoxaccu (ncox accumulator upper byte)......... 290 ncoxclk (ncox clock control) ............................. 289 ncoxcon (ncox control) ...................................... 289 ncoxinch (ncox increment high byte)................. 291 ncoxincl (ncox increment low byte) .................. 291 option_reg (option) ......................................... 161 osccon (oscillator control) ........ ............................. 60 oscstat (oscillator status) ..................................... 61 pcon (power control register) ................................. 69 pcon (power control) ............................................... 69 pie1 (peripheral interrupt enable 1)........................... 77 pie2 (peripheral interrupt enable 2)........................... 78 pie3 (peripheral interrupt enable 3)........................... 79 pir1 (peripheral interrupt register 1) ........................ 80 pir2 (peripheral interrupt request 2) ........................ 81 pir3 (peripheral interrupt request 3) ........................ 82 pmadrl (program memory address)...................... 106 pmcon1 (program memory control 1).................... 107 pmcon2 (program memory control 2).................... 108 pmdath (program memory data) ........................... 106 pmdatl (program memory data)............................ 106 pmdrh (program memory address) ....................... 106 porta...................................................................... 112 portb...................................................................... 116 portc ..................................................................... 120 pwmxcon (pwm control)....................................... 267 pwmxdch (pwm control)....................................... 268 pwmxdcl (pwm control) ....................................... 268 rcreg ..................................................................... 253 rcsta (receive status and control)....................... 246 spbrgh................................................................... 248 spbrgl ................................................................... 248 special function, summary ........................................ 27 sspxadd (msspx address and baud rate, i 2 c mode) ......................................................... 233 sspxcon1 (msspx control 1) ................................ 230 sspxcon2 (sspx control 2) ................................... 231 sspxcon3 (sspx control 3) ................................... 232 sspxmsk (sspx mask) ........................................... 233 sspxstat (sspx status) ........................................ 228 status...................................................................... 19 t1con (timer1 control)........................................... 171 t1gcon (timer1 gate control) ............................... 172 t2con...................................................................... 177 trisa (tri-state porta)......................................... 112 trisb (tri-state portb)......................................... 116 trisc (tri-state portc) ........................................ 120 txsta (transmit status and control) ...................... 245 vregcon (voltage regulator control) ..................... 87 wdtcon (watchdog timer control) ......................... 91 wpua (weak pull-up porta) ................................. 114 wpub (weak pull-up portb) ................................. 118 reset .............................................................................. 317 reset................................................................................... 63 reset instruction ................................................................. 66 resets................................................................................. 63 associated registers.................................................. 70 revision history................................................................ 407 s software simulator (mplab sim) .................................... 395 spbrg register................................................................. 28 spbrgh register ............................................................ 248 spbrgl register............................................................. 248 special function registers (sfrs)..................................... 27 spi mode (msspx) associated registers................................................ 190 spi clock.................................................................. 186 sspov ............................................................................. 217 sspov status flag .......................................................... 217 sspxadd register........................................................... 233 sspxcon1 register ........................................................ 230 sspxcon2 register ........................................................ 231 sspxcon3 register ........................................................ 232 sspxmsk register........................................................... 233 sspxstat register ......................................................... 228 r/w bit ..................................................................... 195 stack................................................................................... 34 accessing ................................................................... 34 reset .......................................................................... 36 stack overflow/underflow .................................................. 66 standard operating conditions ........................................ 321 status register ............................................................... 19 subwfb .......................................................................... 319 t t1con register ......................................................... 27, 171 t1gcon register ............................................................ 172 t2con (timer2) register................................................. 177 t2con register ................................................................. 27 temperature indicator associated registers................................................ 132 temperature indicator module.......................................... 131 thermal considerations.................................................... 332 timer0 .............................................................................. 159 associated registers................................................ 161 operation.................................................................. 159 specifications ........................................................... 339 timer1 ...................................................................... 162, 163 associated registers ................................................. 173 asynchronous counter mode ................................... 165 reading and writing ......................................... 165 clock source selection ............................................ 164 interrupt .................................................................... 167 operation.................................................................. 164 operation during sleep ............................................ 167 prescaler .................................................................. 165 specifications ........................................................... 339 timer1 gate selecting source .............................................. 165 tmr1h register....................................................... 163 tmr1l register ....................................................... 163 timer2 .............................................................................. 175 associated registers ................................................. 177 timers timer1 t1con ............................................................. 171 t1gcon........................................................... 172 timer2 t2con ............................................................. 177 timing diagrams acknowledge sequence ........................................... 219
pic16(l)f1508/9 ds40001609b-page 414 ? 2011-2013 microchip technology inc. adc conversion ....................................................... 342 asynchronous reception .......................................... 242 asynchronous transmission ..................................... 238 asynchronous transmission (back to back) ............ 238 auto wake-up bit (wue) during normal operation . 255 auto wake-up bit (wue) during sleep .................... 255 automatic baud rate calibration .............................. 253 baud rate generator with clock arbitration ............. 212 brg reset due to sda arbitration during start condition........................................................... 223 brown-out reset (bor) ........................................... 337 brown-out reset situations ........................................ 65 bus collision during a repeated start condition (case 1) ............................................................ 224 bus collision during a repeated start condition (case 2) ............................................................ 224 bus collision during a start condition (scl = 0) ..... 223 bus collision during a stop condition (case 1) ....... 225 bus collision during a stop condition (case 2) ....... 225 bus collision during start condition (sda only) ...... 222 bus collision for transmit and acknowledge............ 221 clc propagation timing........................................... 340 clkout and i/o....................................................... 336 clock synchronization .............................................. 209 clock timing ............................................................. 333 comparator output ................................................... 152 fail-safe clock monitor (fscm) ................................. 59 first start bit timing ................................................. 213 i 2 c bus data ............................................................. 348 i 2 c bus start/stop bits.............................................. 348 i 2 c master mode (7 or 10-bit transmission) ............ 216 i 2 c master mode (7-bit reception) ........................... 218 i 2 c stop condition receive or transmit mode ......... 220 int pin interrupt.......................................................... 74 internal oscillator switch timing................................. 54 repeat start condition.............................................. 214 reset start-up sequence............................................ 67 reset, wdt, ost and power-up timer ................... 337 send break character sequence ............................. 256 spi master mode (cke = 1, smp = 1) ..................... 345 spi mode (master mode) .......................................... 186 spi slave mode (cke = 0) ....................................... 346 spi slave mode (cke = 1) ....................................... 346 synchronous reception (master mode, sren) ....... 260 synchronous transmission....................................... 258 synchronous transmission (through txen) ........... 258 t2_match .................................................................. 176 timer0 and timer1 external clock ........................... 339 timer1 incrementing edge........................................ 167 timer2....................................................................... 175 two-speed start-up .................................................... 57 usart synchronous receive (master/slave) ......... 344 usart synchronous transmission (master/slave) . 344 wake-up from interrupt ............................................... 86 timing parameter symbology........................................... 333 timing requirements i 2 c bus data ............................................................. 349 i2c bus start/stop bits ............................................. 348 spi mode .................................................................. 347 tmr0 register .................................................................... 27 tmr1h register ................................................................. 27 tmr1l register .................................................................. 27 tmr2 register .................................................................... 27 tris .................................................................................. 320 trisa register ........................................................... 27, 112 trisb register........................................................... 27, 116 trisc ............................................................................... 119 trisc register........................................................... 27, 120 two-speed clock start-up mode........................................ 56 txreg ............................................................................. 237 txreg register ................................................................. 28 txsta register.......................................................... 28, 245 brgh bit .................................................................. 248 u usart synchronous master mode requirements, synchronous receive .............. 344 requirements, synchronous transmission...... 344 timing diagram, synchronous receive ........... 344 timing diagram, synchronous transmission... 344 v v ref . s ee adc reference voltage vregcon register ........................................................... 87 w wake-up on break ............................................................ 254 wake-up using interrupts ................................................... 85 watchdog timer ................................................................. 89 watchdog timer (wdt)...................................................... 66 associated registers .................................................. 92 modes......................................................................... 90 specifications ........................................................... 338 wcol ....................................................... 212, 215, 217, 219 wcol status flag.................................... 212, 215, 217, 219 wdtcon register ............................................................. 91 wpua register................................................................. 114 wpub register................................................................. 118 write protection .................................................................. 45 www address ................................................................. 415 www, on-line support ................................................... 2, 6
? 2011-2013 microchip technology inc. ds40001609b-page 415 pic16(l)f1508/9 the microchip web site microchip provides online support via our www site at www.microchip.com . this web site is used as a means to make files and information easily available to customers. accessible by using your favorite internet browser, the web site contains the following information: ? product support ? data sheets and errata, application notes and sample programs, design resources, user?s guides and hardware support documents, latest software releases and archived software ? general technical support ? frequently asked questions (faq), technical support requests, online discussion groups, microchip consultant program member listing ? business of microchip ? product selector and ordering guides, latest microchip press releases, listing of seminars and events, listings of microchip sales offices, distributors and factory representatives customer change notification service microchip?s customer notification service helps keep customers current on microchip products. subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. to register, access the microchip web site at www.microchip.com . under ?support?, click on ?customer change notification? and follow the registration instructions. customer support users of microchip products can receive assistance through several channels: ? distributor or representative ? local sales office ? field application engineer (fae) ? technical support ? development systems information line customers should contact their distributor, representative or field application engineer (fae) for support. local sales offices are also available to help customers. a listing of sales offices and locations is included in the back of this document. technical support is available through the web site at: http://microchip.com/support
pic16(l)f1508/9 ds40001609b-page 416 ? 2011-2013 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip product. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to: technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds40001609b pic16(l)f1508/9 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
? 2011-2013 microchip technology inc. ds40001609b-page 417 pic16(l)f1508/9 product identification system to order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office . part no. x /xx xxx pattern package temperature range device device: pic16f1508, pic16lf1508, pic16f1509, pic16lf1509 tape and reel option: blank = standard packaging (tube or tray) t = tape and reel (1) temperature range: i= -40 ? c to +85 ? c(industrial) e= -40 ? c to +125 ? c (extended) package: (2) ml = qfn p = plastic dip so = soic ss = ssop pattern: qtp, sqtp, code or special requirements (blank otherwise) examples: a) pic16lf1508t - i/so tape and reel, industrial temperature, soic package b) pic16f1509 - i/p industrial temperature pdip package c) pic16f1508 - e/ml 298 extended temperature, qfn package qtp pattern #298 note 1: tape and reel identifier only appears in the catalog part number description. this identifier is used for ordering purposes and is not printed on the device package. check with your microchip sales office for package availability with the tape and reel option. 2: for other small form-factor package availability and marking information, please visit www.microchip.com/packaging or contact your local sales office. [x] (1) tape and reel option -
pic16(l)f1508/9 ds40001609b-page 418 ? 2011-2013 microchip technology inc. notes:
? 2011-2013 microchip technology inc. ds40001609b-page 419 information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application meets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safety applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting from such use. no licenses are conveyed, implicitly or otherwise, under any microchip intellectual property rights. trademarks the microchip name and logo, the microchip logo, dspic, flashflex, k ee l oq , k ee l oq logo, mplab, pic, picmicro, picstart, pic 32 logo, rfpic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. filterlab, hampshire, hi-tech c, linear active thermistor, mtp, seeval and the embedded control solutions company are registered trademarks of microchip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. analog-for-the-digital age, application maestro, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dspicworks, dsspeak, ecan, economonitor, fansense, hi-tide, in-circuit serial programming, icsp, mindi, miwi, mpasm, mpf, mplab certified logo, mplib, mplink, mtouch, omniscient code generation, picc, picc-18, picdem, picdem.net, pickit, pictail, real ice, rflab, select mode, sqi, serial quad i/o, total endurance, tsharc, uniwindriver, wiperlock, zena and z-scale are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. gestic and ulpp are registered trademarks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2011-2013, microchip technology incorporated, printed in the u.s.a., all rights reserved. printed on recycled paper. isbn: 9781620772621 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the most secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal methods used to breach the code protecti on feature. all of these methods, to our knowledge, require using the microchip products in a manner outs ide the operating specifications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconductor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are co mmitted to continuously improvin g the code protection features of our products. attempts to break microchip?s code protection feature ma y be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microperipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem certified by dnv == iso/ts 16949 ==
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